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Associate Professor Department of
Electrical Eng. and Computer Science Also affiliated with Center for Ultra Scale
Computing and Information Security (CUCIS) |
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Office: Tech Building, L475 (map to office) Dept. of EECS Evanston, IL 60208-3118 Fax: (847) 467-4144 Lab: Tech Building, L458 Phone: (847) 467-4610 |
Research Interest: Computer Architecture/Microarchitecture
My research is on holistic computer architectures. Specifically,
my group works on understanding the effects of applications, users, and
underlying technologies on architectures and vice versa. These efforts include incorporating holistic effects into architecture
design process (for example, investigating the impact of architectures on
users, utilizing biological information to make architectural decisions,
estimating profitability of a design); application-specific processors (for
example, architectures and compilers for networking, security, and data
mining); and physical-aware architectures (architectures for minimizing the
power consumption, reducing operating temperatures, and mitigating the
effects of process variations). More information about my current/past project can be found here. Selected Recent Publications
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FeatherWeight: Low-cost Optical Arbitration with QoS Support (MICRO11) -
Hardware/Software Techniques for DRAM Thermal Management (HPCA11) -
Quantifying and Coping with Parametric Variations in 3D-Stacked Microarchitectures (DAC10) - FlexiShare: Energy-Efficient Nanophotonic Crossbar
Architecture through Channel Sharing (HPCA10) - Into
the Wild: Studying Real User Activity Patterns to Guide Power Optimization
for Mobile Architectures (MICRO09)
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Selective Wordline Voltage Boosting for Caches to
Manage Yield under Process Variations (DAC09) -
Firefly: Illuminating Future Network-on-Chip with Nanophotonics (ISCA09) - Power
to the People: Leveraging Human Physiological Traits to Control
Microprocessor Frequency (MICRO08)
[Nominated for Best Paper Award] -
Evaluating the Effects of Cache Redundancy on Profit (MICRO08) -
Learning and Leveraging the Relationship between Architecture-Level
Measurements and Individual User Satisfaction (ISCA08) -
Efficient System Design Space Exploration Using Machine Learning Techniques (DAC08) - A
Power and Temperature Aware DRAM Architecture (DAC08) -
PICSEL: Measuring User-Perceived Performance to Control Dynamic Frequency
Scaling (ASPLOS08) - Variable
Latency Caches for Nanoscale Processor (SC07) [Winner of
best student paper award]
- Microarchitectures for Managing Chip Revenues under
Process Variations (CAL07) -
Yield-Aware Cache Architectures (MICRO06) - MineBench: A Benchmark Suite for Data Mining Workloads (IISWC06) -
Thermal Management of On-Chip Caches Through Power Density Minimization (MICRO05) - A Case
for Clumsy Packet Processors (MICRO04) Graduate Students Advised/Co-advised
Emre Karaman, PhD Prabhat Kumar*, PhD Utku Pamuksuz, PhD Benjamin Scholbrock, PhD Matt Schuchhardt, PhD Kaicheng Zhang**,
PhD *co-advised with Prof. Choudhary **co-advised with Prof. Ogrenci-Memik Alumni
PhD
- Pan Yan,
2011 Thesis
title: Leveraging Nanophotonics in Future Many-core Processors. Position:
Technology Department at Globalfoundries, Inc. - Abhishek Das (co-advised with Prof. A. Choudhary), 2010 Thesis
title: Microarchitectural Approaches for Optimizing Power and Profitability
in Multicore Processors. Position: Intel Architecture Group. - Alex Shye, 2010 Thesis
title: Incorporating the End User in Computer Design and Optimization.
Position: Qualcomm Research, Bay Area R&D. - Yu Zhang,
2010 Thesis
title: Adaptive On-Chip Networks and Their Impact on Processor Architectures.
Position: Research and Development Department, Bloomberg L.P. - Serkan Ozdemir, 2009 Thesis
Title: Mitigating the Effects of Process Variations through
Microarchitectural Techniques. Position: Intel Barcelona Research Center - Berkin Ozisikyilmaz
(co-advised with Prof. A. Choudhary), 2009 Thesis
title: Analysis, Characterization and Design of Data Mining Applications and
Applications to Computer Architecture. Position: NetApp
- Arindam Mallik, 2008 Thesis
Title: Holistic Computer Architectures based on Application, User, and
Process Characteristics. Position: IMEC MS
- Anitha Mohan (co-advised with Prof.
S. O. Memik), 2010 Thesis
Title: Yield improvement using cache SRAM array supply lowering and selective
wordline voltage boosting mechanisms - Matthew Erler (co-advised with Prof.
Y. Ismail), 2007 Thesis
Title: TAP Cache: Temperature-Aware Placement for Caches - David Nguyen, 2005 Thesis
Title: Reconfigurable Architectures For Network Intrusion Detection |
