I am a PhD student at the Electrical Engineering and Computer Science Department at Northwestern University. My research interests is compiler techniques to support timing speculative processor architecture and I am advised by Professor Russ Joseph. I received a B.S. degree in Computer Science and Engineering from Bucknell University in 2007.
Exploring Circuit Timing-aware Languages and Compilation,
G. Hoang, R. Findler, R. Joseph
Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2011.
- A Case for Alternative Nested Paging Models for Virtualized Systems,
G. Hoang, C. Bae, J. Lange, L. Zhang, P. Dinda, R. Joseph
Computer Architecture Letters, Volume 9, Number 1, January-June, 2010.