Welcome to the home page of the Cadence Users Group at the Electrical Engineering and Computer Science Department of Northwestern University.

This page contains information about the Cadence design tools used in classes in the Department of Electrical Engineering and Computer Science. Students obtain practical experience in electronics design using state-of-the-art CAD tools, computing and laboratory facilities.

Program Goals:

 

  • To allow students to gain hands on experience in modern digital design techniques, including HDL design, synthesis, and implementation.
  • To supplement current curriculum with leading industrial design tools.
  • To provide environment for practical real world applications
  • To enable students with the skills required to implement their designs in FPGA/ASICs
  • To enable students with debugging skills necessary to become successful digital designers

 

Value Added Items:

 

Two Silicon Ensemble tutorials

 

Student Projects:

 

Analysis of inversed temperature dependence during dual Vth assignment

Analysis for timing variation due to process variations

A brief report on designing a 64-bit ALU and the use of Cadence physical design tools to obtain spatial power profiles

 

Please check this section for newly added student design projects using Cadence design tools.

 

Classes:

 

Cadence design tools will be used in the following courses:

 

Course

Course Title

Description

EECS 391

VLSI Systems Design

Students will become familiar with the realities of CMOS VLSI design: Proper layout structures, and the impact of fabrication technologies; Methods for optimizing the area, speed, and power of circuit layouts; The use of CAD tools for both schematic and layout of complex CMOS circuits; Methods for testing of circuit designs, both during creation and on individual die; Tradeoffs in device implementation technologies, such as Full-custom, standard cell, gate array, FPGA, PLD. Students will create various custom IC implementations using the Custom IC layout tools from Cadence.

EECS 303

Advanced Digital Design

Upcoming revision, new course content planned:

Students will be introduced to Hardware Description Languages and their mapping to gate level logic structures using Encounter.

EECS 355

ASIC & FPGA Design

Students gain experience writing hardware descriptions in VHDL using several different styles (including behavioral, gate level design and Register Transfer Level Design). They use industry standard computer-aided design tools including Cadence Digital IC design products. Each student will have the opportunity to design several projects individually and work in groups to create larger designs.

 

 

Research Projects:

 

Cadence Design Tools are currently being used for the following research groups:

 

NEW: Parallel Architecture Group at Northwestern: Power dissipation and energy consumption have become one of the most important problems in processor and more generally data center design. While lowering the operational voltage beyond guard-band can dramatically reduce power consumption, it will also introduce timing-errors to the system. However, not all computations and all data need to maintain 100% accuracy. We propose to occasionally relax the reliability guarantees of the hardware layer based on the software requirements. By steering each computation and data to different functional and storage units with different voltage levels, Elastic Fidelity Computing obtains power and energy savings while reaching the reliability targets required by each computational segment. We will use Cadence Digital IC design products to build our hardware model which corelates voltage level and error rate.

NEW: Bio-Inspired Sensors and Optoelectronics Laboratory uses Cadence custom IC design tools to design and develop very high-performance read-out integrated circuits (ROIC) for the next generation focal plane arrays with multiple-megapixel resolution. The ROICs are tailored for novel high-sensitivity imager elements with internal amplification such as the nano-injection detectors, and they offer high versatility, high timing accuracy with low noise levels.

Laboratory of Application and Domain-Specific Computing investigates development of various domain specific programmable processors as well as customized hardware programmable fabrics for high performance and /or low power computing. Implementation and performance analysis of various functional units, memory structures, and interconnect networks is carried out using the Cadence design environment.

Laboratory of Design and Analysis of High-Performance ICs utilizes custom IC design tools for design and modeling of novel high performance circuits. Currently, investigations on thermal modeling of high performance ICs is carried out.

Laboratory of Application Specific Instruction Processors and Microarchitecture investigates the impact of parametric process variations on the timing of processor components and furthermore the resulting variations in chip yields.

 

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"CadenceÔ is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134."

Seda Ogrenci Memik, sedaateecs.northwestern.edu

Last modified:  February 10, 2012