Book Chapters
1. E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik, M.
Sarrafzadeh, Strategically Programmable Systems, The Computer Engineering Handbook, CRC Press, December 2001
2. E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Ogrenci Memik,
M. Sarrafzadeh (J. Cong and J. R. Shinnerl
(editors)), Optimization for Reconfigurable Systems Using Hierarchical
Abstraction, Multilevel Optimization and VLSICAD. Kluwer Academic Publishers,
Journal
1. A. Varrenti, C. Zhou, A. Klock, S. Chyung, J. Long, S.
Ogrenci Memik, M. Grayson, Thermal Sensing with Lithographically Patterned
Bimetallic Thin-Film Thermocouples, IEEE Electron Device Letters, Vol. 32, No.
6, pp. 818-820, 2011
2. A. A. Del Barrio Garcia, S. Ogrenci Memik, M. C.
Molina, J. M. Mendias, R. Hermida,
A Distributed Controller for Managing Speculative Functional Units in High
Level Synthesis, IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems (TCAD), Vol. 30, No. 3,
pp. 350-363, 2011
3. Jieyi Long, Ja-Chun Ku, Seda Ogrenci Memik, Yehea Ismail,
SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced
Delay Variation, IEEE Transactions on Very Large Scale Integration Systems
(TVLSI), Vol. 18, No. 9, pp. 1323-1336, September 2010.
4. Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik, An
Approach for Adaptive DRAM Temperature and Power Management, IEEE Transactions
on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 4, pp. 684-688,
April 2010.
5. Min Ni, Seda Ogrenci Memik, A Fast Heuristic
Algorithm for Multi-Domain Clock Skew Scheduling, IEEE Transactions on Very
Large Scale Integration Systems (TVLSI), Vol. 18, No. 4, pp. 630-637, April
2010.
6. A. Montone, M. D. Santambrogio, D. Sciuto, S.
Ogrenci Memik, Placement and Floorplanning
in Dynamically Reconfigurable FPGAs, ACM Transactions on Reconfigurable
Technology and Systems (TRETS), Vol. 4(1), 2010.
7. Francesco Redaelli, Marco D.
Santambrogio, Seda Ogrenci Memik, An ILP formulation
for the Task Graph Scheduling Problem tailored to bi-dimensional Reconfigurable
Architectures, International Journal on Reconfigurable Computing (IJRC), Vol.
2009, pp. 1-12, 2009.
8. Jieyi Long, Hai Zhou, Seda Ogrenci Memik, EBOARST: An
Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
Algorithm, IEEE Transactions on Computer Aided Design of Integrated Circuits
and Systems (TCAD), Vol. 27, No. 12, pp. 2169-2182, December 2008.
9. Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal,
Pre-synthesis Area Estimation of Reconfigurable Streaming Accelerators, IEEE
Transactions on Computer Aided Design of Integrated Circuits and Systems
(TCAD), Vol. 27, No. 11, pp. 2027-2038, November 2008.
10. R. Mukherjee, S. Liu, S. Ogrenci Memik, S. Mondal, A High-Level Clustering Algorithm Targeting Dual Vdd FPGAs, ACM Transactions on Design Automation of
Electronic Systems (TODAES), Vol. 13, Issue 4, pp. 57-76, September 2008.
11. J. Long, S. Ogrenci Memik, G. Memik, R. Mukherjee, Thermal
Monitoring Mechanisms for Chip Multiprocessors, ACM Transactions on Architecture
and Code Optimization (TACO), Vol. 5, Issue 2, pp. 9-41, August 2008.
12. S. Ogrenci Memik, R. Mukherjee, M. Ni, J. Long, Optimizing
Thermal Sensor Allocation for Microprocessors, IEEE Transactions on Computer
Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 3, pp.
516—527, March 2008.
13. R. Mukherjee, S. Ogrenci Memik, “An Integrated
Approach to Thermal Management in High-Level Synthesis”, IEEE Transactions on
Very Large Scale Integration Systems (TVLSI), Vol. 14, No. 1, pp. 1165—1174,
November 2006.
14. E. Kursun, R. Mukherjee, S.
Ogrenci Memik, Early Quality Assessment for Low Power Behavioral Synthesis,
Journal of Low Power Electronics (JOLPE), Vol. 1, No. 3, pp. 273—285,
December 2005.
15. Srivastava, S. Ogrenci Memik, B.K. Choi, M. Sarrafzadeh,
On Effective Slack Management in Post-Scheduling Phase, IEEE Transactions on
Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No.
4, April 2005.
16. S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, M.
Sarrafzadeh, A Scheduling Algorithm for Optimization and Planning in High-level
Synthesis, ACM Transactions on Design Automation of Electronic Systems
(TODAES), Vol. 10, No. 1, January 2005.
17. E. Bozorgzadeh, S. Ogrenci Memik, X. Yang, M. Sarrafzadeh, Routability-driven
Packing: Metrics and Algorithms for Cluster-based FPGAs, Journal of Circuits,
Systems, and Computers (JCSC), Vol. 13, No. 1, February 2004.
18. S. Ogrenci Memik, A. K. Katsaggelos, M. Sarrafzadeh, FPGA
Implementation and Analysis of an Iterative Image Restoration Algorithm, IEEE
Transactions on Computers, Vol. 52 No.3, March 2003.
19. R. Kastner, A. Kaplan, S. Ogrenci Memik, E. Bozorgzadeh, Instruction Generation for Hybrid
Reconfigurable Systems, ACM Transactions on Design Automation of Electronic
Systems (TODAES), Vol. 7, No. 4, October 2002.
20. Ranjan, K. Bazargan,
Conference
and Workshop
1. S. Liu, S. Ogrenci Memik, Y. Ismail, A Comprehensive Tapered Buffer
Optimization Algorithm for Unified Design Metrics, IEEE International Symposium
on Circuits and Systems (ISCAS), May 15-18, 2011, Rio de Janeiro, Brazil.
2. A. A. Del Barrio Garcia, S. Ogrenci
Memik, M. C. Molina, J. M. Mendias,
R. Hermida, Power Optimization in Heterogenous
Datapaths, Design, Automation and Test in Europe
(DATE), 14-18 March, 2011, Grenoble, France.
3. S. Liu, B. Leung, A. Neckar, S. Ogrenci
Memik, G. Memik, N. Hardavellas, Hardware/Software Techniques for DRAM Thermal
Management, IEEE International Symposium on High-Performance Computer
Architecture Conference (HPCA), February 14-16, 2011, San Antonio, TX.
4. J. Long, A. Klock, C. Zhou, S.
Ogrenci Memik, M. Grayson, IOTA: Towards an Integrated On-chip Thermocouple
Array, International Workshop on Thermal Investigations of ICs and Systems
(THERMINIC), October 6-8, 2010, Barcelona, Spain.
5. B. Leung, C.-H. Wu, S. Ogrenci Memik, S. Mehrotra, An Interior Point Optimization Solver for Real
Time Interframe Collision Detection: Exploring Resource-Accuracy-Platform
Tradeoffs, International Conference on Field Programmable Logic and Its
Applications (FPL), August 31-September 2, 2010, Milan, Italy
6. J. Long, S. Ogrenci Memik, A framework for optimizing
thermoelectric active cooling systems, IEEE/ACM Design Automation Conference
(DAC), 2010, Anaheim, CA
7. Min Ni, Seda Ogrenci Memik, A Revisit to the
Primal-Dual Based Clock Skew Scheduling Algorithm, International Symposium on
Quality Electronic Design (ISQED), March 22-24, 2010, San Jose, CA
8. A Del Barrio, M C Molina, J M Mendias,
R Hermida, S Ogrenci Memik, Using Speculative
Functional Units in High Level Synthesis, Design, Automation and Test in Europe
(DATE), March 8-12, 2010, Dresden, Germany
9. Jieyi Long, Seda Ogrenci Memik, Matthew Grayson, Optimization
of Thin-film Thermoelectric Cooler based On-chip Active Cooling System, Design,
Automation and Test in Europe (DATE), March 8-12, 2010, Dresden, Germany
10. Jieyi Long, Seda Ogrenci Memik, “Optimization of the
Bias Current Network for Accurate On-Chip Thermal Monitoring”, Design,
Automation and Test in Europe (DATE), March 8-12, 2010,
11. Jieyi Long, Seda Ogrenci Memik, “Inversed Temperature
Dependence Aware Clock Skew Scheduling for Sequential Circuits”, Design,
Automation and Test in Europe (DATE), March 8-12, 2010,
12. Francesco Redaelli, Marco Domenico Santambrogio, Vincenzo Rana, Seda Ogrenci
Memik, “Scheduling and 2D Placement Heuristics for Partially Reconfigurable
Systems”, International Conference on Field-Programmable Technology (FPT),
December 9-11 2009, Sydney, Australia
13. C.-H. Wu, S. Ogrenci Memik, S. Mehrotra,
“FPGA Implementation of the Interior-Point Algorithm for Linear Programming
with Applications to Collision Detection”, IEEE Symposium on FPGAs for Custom
Computing Machines (FCCM), April 2009,
14. B. Leung, Y. Pan, C. Schroeder, S. Ogrenci Memik, G.
Memik, M. Hartmann, “Towards an "Early Neural Circuit Simulator": An
FPGA Implementation of Processing In the Rat Whisker System”, International
Conference on Field Programmable Logic and Its Applications (FPL), September
8-10 2008, Heidelberg, Germany
15. S. Liu, S. Ogrenci Memik, Y. Zhang, G. Memik, “An
Approach for Adaptive DRAM Temperature and Power Management”, ACM International
Conference on Supercomputing (ICS), June 7-12, 2008, Kos,
16. J. Long, S. Ogrenci Memik, “Automated Design of
Self-Adjusting Pipelines”, IEEE/ACM Design Automation Conference (DAC), June
8-13, 2008,
17. S. Liu, S. Ogrenci Memik, Y. Zhang, G. Memik, A Power
and Temperature Aware DRAM Architecture, IEEE/ACM Design Automation Conference
(DAC), June 8-13, 2008,
18. M. Ni, S. Ogrenci Memik, Leakage Power-Aware Clock
Skew Scheduling: Converting Stolen Time into Leakage Power Reduction, IEEE/ACM
Design Automation Conference (DAC), June 8-13, 2008,
19. J. Long, H. Zhou, S. Ogrenci Memik,
An O(nlogn) Edge-Based Algorithm for
Obstacle-Avoiding Rectilinear Steiner Tree Construction, ACM International
Symposium on Physical Design (ISPD), April 13-16, 2008,
20. M. Giani, M. Santambrogio, S. Ogrenci Memik, Managing Reconfigurable
Resources in Heterogeneous Cores using Portable Pre-Synthesized Templates,
International Symposium on System-on-Chip, November 19-21, 2007, Tampere,
Finland
21. M. Ni, S. Ogrenci Memik, Early Planning for Clock Skew
Scheduling during Register Binding, IEEE/ACM International Conference on
Computer Aided Design (ICCAD), November 5-8, 2007,
22. J. Long, J. Ku, S. Ogrenci Memik, Y. Ismail, A
Self-Adjusting Clock Tree Architecture to Cope with Temperature Variations [Best Paper Award Finalist], IEEE/ACM
International Conference on Computer Aided Design (ICCAD), November 5-8, 2007,
San Jose, CA
23. M. Santambrogio, V. Rana, S. Ogrenci Memik, U. Acar,
D. Scuito, A Novel SoC
Design Methodology Combining Adaptive Software and Reconfigurable Hardware,
IEEE/ACM International Conference on Computer Aided Design (ICCAD), November
5-8, 2007, San Jose, CA
24. M. Ni, S. Ogrenci Memik, Self-Heating-Aware Optimal
Wire Sizing Under Elmore Delay Model, Design, Automation and Test in Europe
(DATE), April 16-20, 2007, Nice, France
25. V. Rana, M. Santambrogio, D. Scuito, S.
Ogrenci Memik, Combining Hardware Reconfiguration and Adaptive Computation for
a Novel SoC Design Methodology, IEEE International
Conference on Field Programmable Technology (FPT), December 13-15, 2006,
Bangkok, Thailand
26. R. Mukherjee, S. Mondal, S. Ogrenci Memik, “Thermal
Sensor Allocation and Placement for Reconfigurable Systems”, in Proc. IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), November 5-9 2006,
27. R. Mukherjee, S. Ogrenci Memik, “Physical Aware
Frequency Selection for Dynamic Thermal Management in Multi-Core Systems”, in
Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
November 5-9 2006,
28. M. Ni, S. Ogrenci Memik, “Thermal-Induced Leakage
Power Optimization by Redundant Resource Allocation”, in Proc. IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), November 5-9 2006,
29. S. Ogrenci Memik, M. Santambrogio,
G. Agosta, “Adaptive Metrics for System-Level
Functional Partitioning”, in Proc. Forum on Specification and Design Languages
(FDL), September 19-22 2006,
30. S. Mondal, S. Ogrenci Memik, N. Bellas, “Pre-Synthesis
Area Estimation of Reconfigurable Streaming Accelerators”, in Proc.
International Conference on Field Programmable Logic and Applications (FPL),
August 28-30 2006, Madrid, Spain
31. R. Mukherjee, S. Ogrenci Memik, “Systematic
Temperature Sensor Allocation and Placement for Microprocessors”, in Proc.
IEEE/ACM Design Automation Conference (DAC), July 24-28, 2006,
32. R. Mukherjee, S. Mondal, S. Ogrenci Memik, “A Sensor
Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration
Overhead”, in Proc. International Conference on Engineering of Reconfigurable
Systems and Algorithms (ERSA), June 26-29, 2006, Las Vegas, NV
33. S. Mondal, R. Mukherjee, S. Ogrenci Memik, “Fine-Grain
Thermal Profiling and Sensor Insertion for FPGAs”, in Proc. IEEE International
Symposium on Circuits and Systems (ISCAS), May 21-24 2006,
34. S. Mondal, S. Ogrenci Memik, N. Bellas, “Pre-synthesis
Queue Size Estimation of Streaming Data Flow Graphs (Poster Presentation,
2-page extended abstract in the proceedings), IEEE Symposium on FPGAs for
Custom Computing Machines (FCCM), April24-26, 2006, Napa, CA
35. D. Nguyen, G. Memik, S. Ogrenci Memik, and A.
Choudhary, “Real-Time Feature Extraction for High Speed Networks”, in Proc.
International Conference on Field Programmable Logic and Applications (FPL),
August 24-26 2005, Tampere, Finland
36. R. Mukherjee, S. Ogrenci Memik, G. Memik, “Peak
Temperature Control and Leakage Reduction During Binding in High-Level
Synthesis”, in Proc. ACM/IEEE International Symposium on Low Power Electronics
and Design (ISLPED), August 8-10 2005,
37. R. Mukherjee, S. Ogrenci Memik, G. Memik,
“Temperature-aware Resource Allocation and Binding in High-Level Synthesis”, in
Proc. IEEE/ACM Design Automation Conference (DAC), June 13-17 2005,
38. S. Mondal, S. Ogrenci Memik, “A Low Power FPGA Routing
Architecture”, in Proc. IEEE International Symposium on Circuits and Systems
(ISCAS), May 23-26 2005,
39. S. Mondal, S. Ogrenci Memik, “Fine-Grain Leakage
Optimization in SRAM based FPGAs”, in Proc. Great Lakes Symposium on VLSI
(GLSVLSI), April 17-19,
40. R. Jafari, S. Ogrenci Memik,
M. Sarrafzadeh, “Quick Reconfiguration in Clustered Micro-Sequencer”,
International Parallel and Distributed Processing Symposium (IPDPS), in Proc.
Reconfigurable Architectures Workshop (RAW), April 4-5 2005, Denver, CO
41. S. Mondal, S. Ogrenci Memik, D. Das, “Hierarchical LUT
Structures for Leakage Power Reduction” Poster Presentation, ACM International
Symposium on Field Programmable Gate Arrays (FPGA), February 20-22 2005,
42. S. Mondal, S. Ogrenci Memik, “Resource Sharing in
Pipelined CDFG Synthesis”, in Proc. IEEE/ACM Asia-South Pacific Design
Automation Conference (ASP-DAC), January 18-21,
43. R. Mukherjee, S. Ogrenci Memik, “Evaluation of Dual Vdd Fabrics for Low Power FPGAs”, in Proc. IEEE/ACM
Asia-South Pacific Design Automation Conference (ASP-DAC), January 18-21,
44. R. Mukherjee, S. Ogrenci Memik, “Power-driven Design
Partitioning”, in Proc. International Conference on Field-Programmable Logic
and Its Applications (FPL), August 30 –September1 2004, Antwerp, Belgium
45. R. Mukherjee, S. Ogrenci Memik, “Power Management for
FPGAs: Power-driven Design Partitioning” (Poster Presentation, 2-page extended
abstract included in the proceedings), IEEE Symposium on FPGAs for Custom
Computing Machines (FCCM), April 2004,
46. A. Srivastava, S. Ogrenci
Memik, B. K. Choi, M. Sarrafzadeh, “Achieving Design Closure through Delay
Relaxation Parameter ”, in Proc. IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), November 2003, San Jose, CA
47. S. Ogrenci Memik, G. Memik, R. Jafari,
E. Kursun, “Global Resource Sharing for Synthesis of
Control Data Flow Graphs on FPGAs”, in Proc. IEEE/ACM Design Automation
Conference (DAC), June 2003, Anaheim, CA
48. S. Ogrenci Memik, F. Fallah,
“Accelerated SAT-based Scheduling of Control/Data Flow Graphs”, in Proc.
International Conference on Computer Design (ICCD), September 2002,
49. E. Kursun, A. Srivastava, S. Ogrenci Memik, M. Sarrafzadeh, “Early
Evaluation Techniques for Low Power Binding“, in Proc. ACM/IEEE International
Symposium on Low Power Electronics and Design (ISLPED), August 2002, Monterey,
CA
50. E. Bozorgzadeh, S. Ogrenci Memik, R. Kastner, M.
Sarrafzadeh, “Pattern Selection: Customized Block Allocation for
Domain-Specific Programmable Systems”, in Proc. International Conference on
Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2002,
51. S. Ogrenci Memik, F. Fallah,
“Accelerated Boolean Satisfiability-Based Scheduling
for High-Level Synthesis”, IEEE/ACM International Workshop on Logic & Synthesis
(IWLS), June 2002,
52. G. Memik, S. Ogrenci Memik, W. H. Mangione-Smith,
“Design and Analysis of a Layer Seven Network Processor Accelerator Using
Reconfigurable Logic”, in Proc. IEEE Symposium on FPGAs for Custom Computing
Machines (FCCM), April 2002, Napa, CA.
53. E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik and M.
Sarrafzadeh, “Pattern Selection in Programmable Systems” (poster presentation),
ACM International Symposium on Field Programmable Gate Arrays (FPGA), February
2002, Monterey, CA.
54. S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M.
Sarrafzadeh, “A Super-Scheduler for Embedded Reconfigurable Systems”, in Proc.
IEEE/ACM International Conference on Computer Aided Design (ICCAD), November
2001, San Jose, CA
55. R. Kastner, S. Ogrenci Memik, E. Bozorgzadeh, M.
Sarrafzadeh, “Instruction Generation for Hybrid Reconfigurable Systems”, in
Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD),
November 2001, San Jose, CA
56. K. Bazargan, S. Ogrenci, M.
Sarrafzadeh, “Integrating Scheduling and Physical Design into a Coherent
Compilation Cycle for Reconfigurable Computing Architectures”, in Proc.
IEEE/ACM Design Automation Conference (DAC), June 2001, Las Vegas, NV [Best
Paper Award Nomination]
57. S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M.
Sarrafzadeh, “SPS: A Strategically Programmable System”, International Parallel
and Distributed Processing Symposium (IPDPS), Reconfigurable Architectures
Workshop (RAW), April 2001, San Francisco, CA
58. E. Bozorgzadeh, S. Ogrenci Memik, M. Sarrafzadeh, “RPack: Routability-Driven Packing for Cluster-Based FPGAs”, in
Proc. Asia-South Pacific Design Automation Conference (ASP-DAC), January 2001,
59. S. Ogrenci, K. Bazargan, M.
Sarrafzadeh, “Image Analysis and Partitioning for FPGA Mapping”, in Proc. IEEE
Workshop on Signal Processing Systems (SiPS), October
2000, Lafayette, LA
60. K. Bazargan, R. Kastner, S.
Ogrenci, M. Sarrafzadeh, “A C to Hardware/Software Compiler”, (Poster
Presentation, 2-page extended abstract included in the proceedings), IEEE
Symposium on FPGAs for Custom Computing Machines (FCCM), April 2000, Napa
Valley, CA
61. S. Ogrenci, A. K. Katsaggelos, M. Sarrafzadeh, “FPGA
Implementation and Analysis of Image Restoration” (poster presentation), ACM
International Symposium on Field Programmable Gate Arrays (FPGA), February
2000,
Technical
Reports
Realizing
Low Power FPGAs: A Design Partitioning Algorithm for Voltage Scaling and A
Comparative Evaluation of Voltage Scaling Techniques for FPGAs, Electrical and Computer Engineering Department,
Northwestern University, Technical report no. TR-CMPE-05-0001
Part of this material is based upon work supported by the National Science Foundation under Grant No. CNS-0546305, Grant No. CCF-0541337, Grant No. IIS-0536994, Grant No. 0916746, Grant No. IIS-0613568, by the Semiconductor Research Corporation (SRC) Grant No. G00639, and a Research Initiation Grant by the Alumnae of Northwestern.
Any opinions, findings and conclusions or recomendations expressed in this material are those of the
author(s) and do not necessarily reflect the views of the National Science
Foundation (NSF), SRC, or Alumnae of Northwestern.
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