Self-Adjusting Architectures for Improved Performance, Yield, and Reduced Design Time
Gokhan Memik, Yehea Ismail, Russ Joseph, Seda Memik
Department of Electrical Engineering and Computer Science
Recent trends of nanoscale integrated circuits will not be mitigated by contemporary architectural innovations and will introduce significant bottlenecks in the design of future microprocessors. First, the growing complexity of models for high performance circuits make it difficult to identify critical characteristics, which could aid architects in optimizing the design. Second, there is an increasing variability both in the process parameters and in environmental variables such as power supply and temperature. These increasing variations are directly reflected in microprocessor yield statistics as more manufactured chips fail to meet performance targets. Furthermore, it will be difficult if not impossible to recover from these losses with architectural modifications, which do not directly consider the circuit level causes. Without intervention, the design cycle of future processors will be dominated by exhaustive verification related to model complexity and parameter variation.
This project offers a paradigm shift where the design cycle features focused analysis of possible failures and the addition of self-monitoring, self-adjusting mechanisms that can both improve the yield, increase the performance, and reduce the requirements of verification. At the heart of this approach lies the design of flexible architectures that can tolerate variations. Particularly, this project involves generation of: (1) variation-aware architectural models which are based on physical properties and are essential for an initial estimate of the critical segments in the processor and possible failures, as well as tradeoff studies, (2) innovative self-adjusting architectures which consider physical aspects of circuits and can be reconfigured based on in-field readings, (3) algorithms for placement of sensing and monitoring elements on the chip as well as the deployment of the adaptive structures and determination of the adaptation type needed, and (4) circuit synthesis algorithms, which determine how to adjust processors for improved yield and performance. This project directly attacks a critical problem in the microprocessor industry: process variation, and hence would have significant commercial and social benefits. Academic benefits include the close interaction between the design automation, circuits, and architecture researchers and educators. This will open new avenues for learning and present a new set of interesting challenges.
Two recent, vexing trends of nanoscale integrated circuits will not be mitigated by previously proposed architectural innovations and can constitute a significant bottleneck in the design of future microprocessors. First, the models required to fully verify the performance and functionality of high performance circuits are becoming extremely complex, making it difficult to abstract useful characteristics normally considered at the architectural level. With increasing clock frequencies and device density, physical models need to account for low-level phenomena such as magnetic effects, noise and crosstalk, thermal effects, power estimation, skin effects, proximity effects, supply noise, substrate noise and complex clock distribution among many other issues. These models are becoming computationally intractable, leading to either unacceptable design cycle time or to gross approximations that limit the effectiveness of early stage design analysis and render the whole verification process unreliable. The second trend is the increasing variability both in the process parameters and in environmental variables such as the supply and temperature. These increasing variations directly reflect in the yield of the designed microprocessor with more manufactured chips not meeting the performance targets. Furthermore, it will be difficult if not impossible to recover from these losses with architectural modifications, which do not directly consider the circuit level causes.
This project proposes a paradigm shift where the design cycle is not consumed by the verification, but rather more time is put in identifying possible failures within architectural structures and adding self-monitoring, self-adjusting mechanisms that can both improve the yield and reduce the requirements of verification. This effort will require close interaction between the physical design process, the architectural specification, and the circuit synthesis. Flexible architectures that can tolerate variations and readjust are at the heart of this proposal. These adaptive architectures have to be developed with a synergistic knowledge of the relationship between program characteristics and the underlying physical phenomena responsible for variation. By leveraging information collected at runtime, the hardware can choose dynamic configurations, which maximize performance, energy-efficiency, and reliability. This effort will also necessitate innovations in electronic design automation. For example, some statistical estimates of the delay need to be coupled with algorithms to place delay monitoring elements and retiming techniques to adjust the chip post-manufacturing.
Figure 1. Design cycle: (a) Traditional, (b) with self-adjusting implementation.
Overall, the self-adjusting architecture paradigm will change the processor design cycle as depicted in Figure 1. Figure 1(a) shows a traditional design cycle, where the tools at any level use detailed prediction models for the properties of the lower levels. However, with the self-adjusting architectures (Figure 1(b)), the reliance on such predictions is less and problems associated with most static (e.g., manufacturing, delay estimations) or dynamic variation (e.g., magnetic effects, noise and crosstalk, thermal effects) can be handled effectively. In addition, depending on the properties of the processor state and the applications, self-adjusting architectures will configure themselves to achieve increased performance.
Parameter variations due to manufacturing errors will be an unavoidable consequence of technology scaling in future generations. Despite the large impact that power variability will have on future designs, there is a lack of published work that examines architectural implications of this phenomenon - particularly as it relates to power consumption.
With the aid of this grant, we have developed VariPower, a tool for modeling power variability based on a microarchitectural description and floorplan of a chip. In particular, our models are based on layout level SPICE simulations and project power variability for different microarchitectural blocks using statistical analysis. Our modeling infrastructure uses hierarchical descriptions of architectural resources and can be easily tuned to model a wide variety of processor designs. Using VariPower, we can characterize power variability for multicore processors, explore application sensitivity to power variability.
Figure 2. Gate length variation patterns for two sample chips.
· A. Das, B. Ozisikyilmaz, S. Ozdemir, G. Memik, J. Zambreno, A. Choudhary. "Evaluating the Effects of Cache Redundancy on Profit," In Proc. of International Symposium on Microarchitecture (MICRO), Lake Como, Italy, 2008.
· Sami Kirolos, Yehia Massoud, Yehea Ismail. "Accurate Analytical Delay Modeling of CMOS Clock Buffers Considering Power Supply Variations," International Symposium on Circuits and Systems (ISCAS), 2008.
· Sami Kirolos, Yehia Massoud, Yehea Ismail. "Power-Supply-Variation-Aware Timing Analysis of Synchronous Systems," International Symposium on Circuits and Systems (ISCAS), 2008.
· Meng, Ke; Joseph, Russ; Dick, Robert; Shang, Li. "Multi-Optimization Power Management for Chip Multiprocessors," International Conference on Parallel Architectures and Compilation Techniques, 2008.
· A. Das, S. Ozdemir, G. Memik, A. Choudhary. "Evaluating Voltage Islands in CMPs under Process Variations," 25th IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, 2007.
· A. Das, S. Ozdemir, G. Memik, A. Choudhary. "Mitigating the Effects of Process Variations: Architectural Approaches for Improving Batch Performance," Workshop on Architectural Support for Gigascale Integration (ASGI) held in conjunction with International Symposium on Computer Architecture (ISCA), San Diego, CA, 2007.
· B. Lin, A. Mallik, P. Dinda, G. Memik, and R. Dick. "Power Reduction Through Measurement and Modeling of Users and CPUs," ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), San Diego, CA, 2007.
· Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Choudhary. "Microarchitectures for Managing Chip Revenues under Process Variations," IEEE Computer Architecture Letters, v.6, 2007.
· S. Ozdemir, J. C. Ku, A. Mallik, G. Memik, Y. Ismail. "Variable Latency Caches for Nanoscale Processor," Conference for High Performance Computing, Networking, Storage and Analysis (Supercomputing - SC07), Reno, NV [WINNER OF BEST STUDENT PAPER AWARD], 2007.
· Brooks, D; Dick, RP; Joseph, R; Shang, L. "Power, thermal, and reliability modeling in nanometer-scale microprocessors," IEEE MICRO, v.27, 2007, p. 49-62. View record at Web of Science
· J. Ku and Y. Ismail. "On the Scaling of Temperature-Dependent Effects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007.
· J. Ku, Y. Ismail. "Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits," The International Symposium on Low Power Electronics and Design (ISLPED), 2007.
· J. Long, J. Ku, S. Ogrenci Memik, and Y. Ismail. "A Self-Adjusting Clock Tree Architecture to Cope with Environmental Variations," IEEE/ACM International Conference on Computer-Aided Design, 2007.
· Ke Meng, Frank Huebbers, Russ Joseph, and Yehea Ismail. "Modeling and Characterizing Power Variability in Multicore Architectures," IEEE Symposium on Analysis of Software and Systems (ISPASS-2007), 2007.
· Arindam Mallik, Bin Lin, Gokhan Memik, Peter Dinda, Robert Dick. "User-Driven Frequency Scaling," IEEE Computer Architecture Letters, v.5, 2006, p. 61.
· F. Huebbers, A. Dasdan, and Y. Ismail. "Computation of Accurate Interconnect Process Parameter Values for Performance Corners under Process Variations," IEEE/ACM Design Automation Conference (DAC), 2006, p. 797.
· Ke Meng and Russ Joseph. "Process Variation Aware Cache Leakage Management," The International Symposium on Low Power Electronics and Design (ISLPED 2006), 2006, p. -.
· Ke Meng, Frank Huebbers, Russ Joseph, and Yehea Ismail. "Physical Resource Matching Under Power Asymmetry," P=ac2 Conference 2006, IBM TJ Watson Research Center, 2006, p. -.
· S. Ozdemir, D. Sinha, G. Memik, J. Adams, H. Zhou. "Yield-Aware Cache Architectures," IEEE/ACM International Symposium on Microarchitecture (MICRO), Orlando, FL, 2006, p. 15-25.