Patent Disclosures

  1. Y. I. Ismail, E. G. Friedman, and J. L. Neves "Driving Inductive Interconnect Using Cascaded Buffers", IBM Microelectronics, August, 1999.

  2. Y. Ismail and E. G. Friedman, "Model for Simulating Tree Structured VLSI Interconnect", United States Patent, No. 6,460,165, October 1, 2002.

  3. Y. I. Ismail, "Efficient Model Order Reduction Via Multipoint Moment Matching", Northwestern University, Unites States Patent, No. 6,789,237, September 7, 2004.

  4. Y. I. Ismail, C. Amin, M. H. Chowdhury, and C. V. Kashyap, "Realizable Reduction of RLC Circuits Using Node Elimination", Semiconductor Research Corporation (SRC), (patent pending).

  5. M. Ghoneima, M. Khellah, J. Tschanz, Y. Ye, Y. Ismail, V. De, "Achieving Low MCF by Tapering Segment Width In Opposite directions for Adjacent Bus Lines", US Patent Pending, Intel Corporation, 2003.

          Book

  1. Y. I. Ismail and E. G. Friedman "On-Chip Inductance in High Speed Integrated Circuits" Kluwer Academic Publishers, Massachusetts, 2001.

          Special Issue

  1. Y. Ismail and Byron Krauter "On-Chip Inductance in High Speed Integrated Circuits", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 10, No. 6, December 2002. (Guest Editorial)

          Tutorial

  1. "Design and Analysis of High-Speed Integrated Circuits Including On-Chip Inductance", IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 2002.

  2. "High Performance Design Techniques in Nanometer Integrated Circuits", IEEE International Symposium on Circuits and Systems (ISCAS), May 2003.

          Refereed Journal Publications

  1. J. Ku, S. Ozdemir, G. Memik, and Y. Ismail "Thermal Management of On-Chip Caches through Power Density Minimization", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) (accepted, in press).

  2. J. Ku and Y. Ismail, "On the Scaling of Temperature-Dependent Effects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (accepted, in press).

  3. M. Khellah, M. Ghoneima, J. Tschanz, Y. Ye, N. Kurd, J. Barkatullah, Y. Ismail and V. De, "A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors", IEEE Transactions on Circuits and Systems 1: Fundamental Theory and Applications (TCAS1) (accepted, in press).

  4. M. Ghoneima, M. Khellah, J. Tschanz, Y. Ye, Y. Ismail, and V. De, "Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques", IEEE Transactions on Circuits and Systems 1: Fundamental Theory and Applications (TCAS1) vol. 52, no. 9, pp. 1928-1933, September 2006.

  5. M. Chowdhury and Y. Ismail, "Realistic Scalability of Noise in Dynamic Circuits ", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) vol. 14, no. 6, pp. 637-641, September 2006.

  6. M. Ghoneima and Y. Ismail, "Formal Derivation of Optimal Active Shielding for Low-Power On-Chip Buses", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 5, pp. 821-836, May 2006.

  7. M. Ghoneima and Y. Ismail, "Optimum positioning of interleaved repeaters in bidirectional buses", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.24, no.3, pp. 461-469, March 2005.

  8. M. Ghoneima and Y. Ismail, "Utilizing the Effect of Relative Delay on Energy Dissipation in Low-Power On-Chip Buses", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 12, no.12, pp. 1348-1359, December 2004.

  9. C. S. Amin, F. Dartu, and Y. I. Ismail, "Weibull based analytical waveform model", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 8, pp. 1156-1168, August 2005.

  10. M. H. Chowdhury, C. Amin, Y. I. Ismail, "Realizable reduction of Interconnect Circuits Including Self and Mutual Inductances",  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  vol. 24, no. 2, pp. 271-277, February 2005.

  11. Y. I. Ismail and C. Amin, "Computation of Signal Threshold Crossing Times Directly from Higher Order Moments", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 23, no. 8,  pp. 1264-1276, August 2004.

  12. S. Mei and Y. I. Ismail, "Modeling skin and proximity effects with reduced realizable RL circuits", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 12, no. 4, pp. 437-447, April 2004.

  13. Y. I. Ismail, "Improved Model Order Reduction by Using Spacial Information in Moments", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 11, no. 5, pp. 900-908, October 2003.

  14. Y. I. Ismail, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits: Summary", IEEE Circuits and Systems Magazine, pp. 24-28, April 2003 (Invited paper).

  15. S. Mei, C. Amin, and Y. I. Ismail, "Efficient Model Order Reduction Including Skin Effect", IEEE Canadian Journal of Electrical and Computer Engineering, vol. 27, no.4, pp. 189-194, October 2002 (invited paper).

  16. Y. I. Ismail, "Cons and Pros of  On-Chip Inductance", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 10, no. 6, pp. 685-694, December 2002.

  17. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Inductance Effects in RLC Trees", IEEE Journal of Circuits, Systems, and Computers (JCSC), vol. 11, no. 3, pp. 305-321, August 2002.

  18. Y. I. Ismail and E. G. Friedman "On the Extraction of On-Chip Inductance", IEEE Journal of Circuits, Systems, and Computers (JCSC), vol. 12, no. 1, pp. 31-40, February 2003.

  19. Y. I. Ismail and E. G. Friedman, "DTT: Direct Truncation of the Transfer Function-An Alternative For Moment Matching For Tree Structured Interconnect", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no. 2, pp. 131-144, February 2002.

  20. Y. Massoud and Y. I. Ismail, "On-Chip Inductance in High-Speed Integrated Circuits", IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 14 - 21, July 2001 (Invited Paper).

  21. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 9, no. 6, pp. 963-973, December 2001.

  22. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Repeater Insertion in Tree Structured Inductive Interconnect", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (TCASII), vol. CAS-48, no. 5, pp. 471-481, May 2001.

  23. Y. I. Ismail and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 8, no. 2, pp. 195-206, April 2000.

  24. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore Delay for RLC Trees", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 19, no. 1, pp. 83-97, January 2000.

  25. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of Merit to Characterize the Importance of On-Chip Inductance", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 7, no. 4, pp. 442-449, December 1999.

  26. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines", IEEE Transactions on Circuits and Systems 1: Fundamental Theory and Applications (TCASI), vol. CAS-46, no. 8, pp. 950-961, August 1999.

    27. Refereed Conference Publications

  27. A. Shebaita and Y. Ismail, "Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2007.

  28. J. Ku and Y. Ismail, "Attaining Thermal Integrity in Nanometer Chips", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2007 (Invited paper).

  29. J. Ku and Y. Ismail, "A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2007.

  30. D. Khalil and Y. Ismail, "Approximate Frequency Response Models for RLC Power Grids", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2007.

  31. K. Meng, F. Huebbers, R. Joseph, and Y. Ismail, "Modeling and Characterizing Power Variability in Multicore Architecture", Proceeding of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2007.

  32. A. Shebaita, D. Das, Y. Ismail, H. Zhou, and K. Killpak, "Nostra-XTalk: A Predictive Framework for Accurate Static Timing Analysis in UDSM VLSI Circuits", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), March 2007.

  33. A. Shebaita, D. Petranovic, and Y. Ismail, "Importance of Volume Discretization of Single and Coupled Interconnects", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 119-126, November 2006.

  34. D. Sinha, D. Khalil, H. Zhou, Y. Ismail, "A Timing Dependent Power Estimation Framework Considering Coupling", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 401-407, November 2006.

  35. D. Das, A. Shebaita, H. Zhou, K. Killpak, and Y. Ismail, "FA-STAC: A Framework for Fast and Accurate Static Timing A nalysis with Coupling", Proceedings of the IEEE/ACM International Conference on Computer Design (ICCD), pp. October 2006.

  36. K. Meng, F. Huebbers, R. Joseph, and Y. Ismail, "Physical Resouce Matching under Power Asymmetry", P=ac2 Conference, IBM T.J. Watson Research Center, pp. 1-10, October 2006.

  37. F. Huebbers, A. Dasdan, and Y. Ismail, "Computation of Accurate Interconnect Process Parameter Values for Performance Corners under Process Variations", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 797-800, June 2006.

  38. M. Ghoneima, Y. Ismail, M. Khellah, and V. De, "Reducing the Data Switching Activity of Serialized Datastreams", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1015-1018, May 2006.

  39. D. Khalil and Y. Ismail, "Optimum Sizing of Power Grids for IR Drop", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 481-484, May 2006.

  40. J. Ku, S. Ozdemir, G. Memk, Y. Ismail, "Power Density Minimization for Highly-Associative Caches in Embedded Processors", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 100-104, April-May 2006.

  41. M. Ghoneima, M. Khellah, J. Tschanz, Y. Ismail, and V. De, "Reducing the Data Switching Activity on Serial Link Buses", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 425-432, March 2006.

  42. J. Ku and Y. Ismail, "Area Optimization for Leakage Reduction and Thermal Stability in Nanometer Scale Technologies", Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 231-236, January 2006 (Invited paper).

  43. M. Ghoneima, M. Khellah, J. Tschanz, Y. Ismail and V. De, "Serial Link Bus: A Low Power On-Chip Bus Architecture", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 541-546, November 2005.

  44. A. Shebaita, C. Amin, F. Dartu, Y. Ismail, "Expanding the Frequency Range of AWE via Time Shifting",  Proceedings of  the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 935-938, November 2005.

  45. J. Ku, S. Ozdemir, G. Memik, Y. Ismail, "Thermal Management of On-Chip Caches Through Power Density Minimization", Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 283-293, November 2005.

  46. M. Ghoneima, E. Atoofian, A. Baniasadi, and Y. Ismail, "Low Power Prediction Based Data Transfer Architecture", Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 313-316, September 2005.

  47. J. Ku, M. Ghoneima, and Y. Ismail, "The Importance of Including Thermal Effects in Estimating the Effectiveness of Power Reduction Techniques",  Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 301-304, September 2005.

  48. M. Khellah, M. Ghoneima, J. Tschanz, Y. Ye, N. Kurd, J. Barkatullah, Y. Ismail, and V. De, "A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors", Proceedings of the 2005 IEEE International Conference on Computer Design (ICCD), pp. 253-257, October 2005.

  49. G. Memik, M. Chowdhury, A. Mallik, Y. Ismail, "Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files", Proceedings of the IEEE/ACM International Conference on Dependable Systems and Networks (DSN), pp. 770-779, June-July 2005.

  50. C. S. Amin, Y. I. Ismail, and F. Dartu, "Piece-wise Approximations of RLCK Circuit Responses using Moment Matching", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp.927-932, June 2005.

  51. C. S. Amin, Y. I. Ismail, F. Dartu, and N. Menezes, "Statistical Timing, How Simple Can it Get? ", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 652-657, June 2005.

  52. M. Ghoneima, M. Khellah, J. Tscahnz, Y. Ismail, and V. De, "Skewing Adjacent Line Repeaters to Reduce the Delay and Energy Dissipation of On-Chip Buses", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 592-595, May 2005.

  53. M. Ghoneima and Y. Ismail, "Accurate Decoupling of Coupled On-Chip Buses", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4146-4149, May 2005.

  54. C. S. Amin, Y. I. Ismail, F. Dartu, and N. Menezes, "Simplified Statistical Timing ", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2005.

  55. N. Hassan, M. Ghoneima, and Y. I. Ismail, "Physical Limitations of On-Chip Interconnect",  Proceedings of the IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 13-19, April 2005.

  56. Y. I. Ismail and C. S. Amin, "Computation of Signal Threshold Crossing Times Directly from Higher Order Moments", Proceedings of the IEEE/ACM  International Conference on Computer-Aided Design (ICCAD), pp. 246-253, November 2004.

  57. C. S. Amin, F. Dartu, and Y. I. Ismail, "Modeling Unbuffered Latches for Timing Analysis", Proceedings of  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 254-260, November 2004.

  58. M. Ghoneima and Y. Ismail, "Formal Derivation of Optimal Active Shielding for Low-Power On-Chip Buses", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 800-807, November 2004.

  59. M. H. Chowdhury, Y. I. Ismail, "Analysis of Noise and its Scalability in Dynamic Circuits", Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 505-508, October, 2004.

  60. M. Ghoneima and Y. Ismail, "Low-Power On-Chip Bus Architecture Using Dynamic Relative Delays", Proceedings of the IEEE SOC Conference (SOCC), pp. 233-236, September 2004.

  61. M. Ghoneima and Y. Ismail, "Utilizing the Effect of Relative Delay on Energy Dissipation in Low-Power On-Chip Buses", Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp.66-69, August 2004.

  62. M. Ghoneima and Y. Ismail, "Effect Of Relative Delay On The Dissipated Energy In Coupled Interconnects", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp. II-525-8, May 2004.

  63. M. Ghoneima and Y. Ismail , "Low Power Coupling-Based Encoding For On-Chip Buses", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. II-325-8, May 2004.

  64. D. Dai, W. Wang, and Y. Ismail , "Powder-Based Fabrication Techniques Of Single-Wall Carbon Nanotube Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol.3, pp. III-701-4, May 2004.

  65. M. H. Chowdhury, Y. I. Ismail, "Realistic Scalability of Noise in Dynamic Circuits",  IEEE International Workshop on System-On-Chip for Real Time Application (IWSOC), Canada, July 2004.

  66. M. H. Chowdhury, Y. I. Ismail, "Possible noise failure modes in static and dynamic circuits",  IEEE International Workshop on System-On-Chip for Real Time Application (IWSOC), pp. 123-126, July 2004.

  67. S. Mei, J. Kawa, C. Chiang, Y. Ismail, "An Accurate Low Iteration Algorithm for Effective Capacitance Computation",  IEEE International Workshop on System-On-Chip for Real Time Application (IWSOC), pp. 99-104,  July 2004.

  68. C. S. Amin, F. Dartu, Y. I. Ismail, "Weibull Based Analytical Waveform Model", Proceedings of  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 161-168, November 2003.

  69. C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, "Realizable RLCK Circuit Crunching", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 226-231, June 2003.

  70. S. Mei, C. Amin, and Y. I. Ismail, "Efficient Model Order Reduction Including Skin Effect", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 232-237, June 2003.

  71. M. Ghoneima and Y. Ismail, "Optimum positioning of interleaved repeaters in bidirectional buses", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 586-591, June 2003.

  72. M. H. Chowdhury, C. S. Amin, Y. I. Ismail, C. V. Kashyap, and B. L. Krauter, "Realizable Reduction of RLC Circuits Using Node Elimination", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol III, pp. 494-497, 2003.

  73. S. Mei and Y. Ismail, "Modeling skin effect with reduced decoupled R-L circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 588-591, Thailand, 2003.

  74. N. Mahmoud, Y. Ismail, "Accurate Rise Time And Overshoot Estimation In RLC Interconnects", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol.5, pp. V-477-80, Thailand, 2003.

  75. M. H. Chowdhury, C. Amin, Y. I. Ismail, C. V. Kashyap, and B. L. Krauter, "Realizable Reduction of RLC Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS),  vol.3, pp. III-494-97, May  2003 (Invited paper).

  76. M. H. Chowdhury and Y. I. Ismail, "Analysis of Coupling Noise in Dynamic Circuits", Proceedings of the IEEE International Workshop on System on Chip (IWSOC), pp. 320-325, 2003.

  77. Y. I. Ismail, "Efficient Model Order Reduction via Multi-point Moment Matching", Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 767-774, November 2002.

  78. Y. I. Ismail, "Evaluating Noise Pulses in RLC Networks", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), V-653-6, vol.5, 2002.

  79. M. H. Chowdhury, Y. I. Ismail, C. V. Kashyap, and B. L. Krauter, "Performance Analysis of Deep Sub micron VLSI Circuits in the Presence of Self and Mutual Inductance", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 197-200, 2002.

  80. S. Mei and Y. I. Ismail, "Efficient Model Order Reduction Including Skin Effect", IEEE International Workshop on System-On-Chip for Real Time Application (IWSOC), pp. 189-192, July 2002 (Invited paper).

  81. M. H. Chowdhury, S. Hsien, and Y. I. Ismail, "Circuit and Physical Level Challenges in SoC Circuits", IEEE World Multi-Conference on Systemics, Cybernetics and Informatics, June 2001 (Best paper award).

  82. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks", IEEE Workshop on Signal Processing Systems, pp. 642-652, October 2000.

  83. Y. I. Ismail and E. G. Friedman, "Fast and Accurate Simulation of Tree Structured Interconnect", IEEE Midwest Symposium on Circuits and Systems, vol. 3, pp. 1130-1134, August 2000.

  84. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks", IEEE Workshop on Signal Processing Systems, Design and Implementation (SiPS), pp. 643-652, October 2000.

  85. Y. I. Ismail and E. G. Friedman "Sensitivity of Interconnect Delay to On-Chip Inductance", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 403-407,  May 2000.

  86. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Repeater Insertion in Tree Structured Inductive Interconnect", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 420-424, November 1999.

  87. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Optimizing RLC Tree Delays by Employing Repeater Insertion", Proceedings of the IEEE ASIC Conference, pp. 14-18, September 1999.

  88. Y. I. Ismail, E. G. Friedman, and Jose L. Neves, "Equivalent Elmore Delay for RLC Trees", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 715-720, June 1999.

  89. Y. I. Ismail and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 721-724, June 1999.

  90. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Signal Waveform Characterization in RLC Trees", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 190-193, May 1999.

  91. Y. I. Ismail and E. G. Friedman, "Repeater Insertion in RLC Lines for Minimum Propagation Delay", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 404-407, May 1999.

  92. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Inductance Effects in RLC Trees", Proceedings of the IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 56-59, March 1999.

  93. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Transient Power in CMOS Gates Driving LC Transmission Lines", Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 377-383, September 1998.

  94. Y. I. Ismail and E. G. Friedman, "Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect", Proceedings of the IEEE ASIC Conference, pp. 369-373,September 1998.

  95. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Power dissipated by CMOS Gates Driving Lossless Transmission Lines", Proceedings of the IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 139-141, August 1998.

  96. Y. I. Ismail, E. G. Friedman, and Jose L. Neves, "Figures of Merit to Characterize the Importance of On-Chip Inductance", Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 560-565, June 1998.

  97. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Performance Criteria for Evaluating the Importance of On-Chip Inductance", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 244-247, May 1998.

  98. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines", Proceedings of the IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 39-44, February 1998.

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