Publications

Links to my DBLP Entry and Google Scholar Entry.

According to Google Scholar, as of November 2017 my citation count is 2782, my H-index is 19 and my G-index is 51.

 

2018

Unconventional Parallelization of Nondeterministic Applications

E. A. Deiana, V. St-Amour, P. Dinda, N. Hardavellas and S. Campanoni

23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Williamsburg, VA, March 2018

Acceptance rate 17%

 

2017

POSTER: The Liberation Day of Nondeterministic Programs

E. A. Deiana, V. St-Amour, P. Dinda, N. Hardavellas and S. Campanoni

26th International Conference on Parallel Architectures and Compilation Techniques (PACT), Portland, OR, September 2017

 

VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder

A. M. Gok and N. Hardavellas

27th ACM Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, May 2017

Acceptance rate 24%

 

Harnessing Path Divergence for Laser Control in Data Center Networks

Y. Demir, N. Terzenidis, H. Han, D. Syrivelis, G. T. Kanellos, N. Hardavellas, N. Pleros, S. Kandula, and F. Bustamante

In Proceedings of the 2017 IEEE Photonics Society Summer Topical Meeting Series (IEEE SUM), Optical Switching Technologies for Datacom and Computercom Applications (OSDC), San Juan, Puerto Rico, July 2017

Invited Paper

 

Temporal Approximate Function Memoization

G. Tziantzioulis, H. Han, N. Hardavellas and S. Campanoni

In 6th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2017

 

Soft Dependences: Who They Are, What They Look Like, and How to Satisfy Them

Enrico A. Deiana, Vincent St-Amour, Peter Dinda, Nikos Hardavellas, Simone Campanoni

In 6th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2017

 

Think Green – Turn Off Lights

N. Terzenidis, H. Han, D. Syrivelis, G. T. Kanellos, Y. Demir, J. Gu, N. Pleros, S. Kandula, N. Hardavellas and F. Bustamante

In 6th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2017

 

VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder

A. M. Gok and N. Hardavellas

In 6th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2017

 

Energy Proportional Photonic Interconnects

Y. Demir and N. Hardavellas

In 12th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Stockholm, Sweden, January 2017

 

Techniques for Energy Proportionality in Optical Interconnects

Y. Demir and N. Hardavellas

Photonic Interconnects for Computing Systems, G. Nicolescu, S. Le Beux, M. Nikdast, and J. Xu (Eds.), The River Publishers' Series in Optics and Photonics, River Publishers, 2017

 

2016

Evaluation of K-Means Data Clustering Algorithm on Intel Xeon Phi

S. Lee, W.-k. Liao, A. Agrawal, N. Hardavellas and A. Choudhary

In Proceedings of the 3rd Workshop on Advances in Software and Hardware for Big Data to Knowledge Discovery (ASH), co-located with the IEEE Conference on Big Data (IEEE BigData), Washington, D.C., December 5-8, 2016

 

Energy Proportional Photonic Interconnects

Y. Demir and N. Hardavellas

In ACM Transactions on Architecture and Code Optimization (ACM TACO), Vol. 13(5), December 2016

 

SLaC: Stage Laser Control for a Flattened Butterfly Network

Y. Demir and N. Hardavellas

In Proceedings of the 22nd IEEE International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, March 2016

Acceptance rate 22%

 

Lazy Pipelines: Enhancing Quality in Approximate Computing

G. Tziantzioulis, A. M. Gok, S M Faisal, N. Hardavellas, S. Ogrenci-Memik, and S. Parthasarathy

In Proceedings of the Design, Automation, and Test in Europe (DATE), Dresden, Germany, March 2016

Acceptance rate 24%

 

Towards Energy-Proportional Optical Interconnects

Y. Demir and N. Hardavellas

In Proceedings of the 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS), Dresden, Germany, March 2016

Invited Paper

 

Energy-Proportional Photonic Networks with Stage Laser Control

H. Han, Y. Demir, N. Hardavellas, F. Bustamante and S. Kandula

In 5th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2016

 

Temporal Approximate Function Memoization

G. Tziantzioulis, H. Han, N. Hardavellas and S. Campanoni

In 5th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2016

 

Lazy Pipelines: Enhancing Quality in Approximate Computing

G. Tziantzioulis, A. M. Gok, S M Faisal, N. Hardavellas, S. Ogrenci-Memik and S. Parthasarathy

In 5th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2016

 

2015

Edge Importance Identification for Energy Efficient Graph Processing

S M Faisal, G. Tziantzioulis, A. M. Gok, S. Parthasarathy, N. Hardavellas, and S. Ogrenci-Memik

In Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData), Santa Clara, CA, October 2015

Acceptance rate 18%

 

SCP: Synergistic Cache Compression and Prefetching

B. Patel, G. Memik and N. Hardavellas

In Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD), New York City, NY, October 2015

Acceptance rate 31%

 

Parka: Thermally Insulated Nanophotonic Interconnects

Y. Demir and N. Hardavellas
In Proceedings of the 9th International Symposium on Networks-on-Chip (NOCS), Vancouver, Canada, September 2015
Acceptance rate 25%

 

b-HiVE: A Bit-Level History-Based Error Model with Value Correlation for Voltage-Scaled Integer and Floating Point Units
G. Tziantzioulis, A. M. Gok, S. M. Faisal, N. Hardavellas, S. Memik, and S. Parthasarathy
In Proceedings of the Design Automation Conference (DAC), San Francisco, CA, June 2015

Acceptance rate 18%

Software: SoftInj, a software fault injection library that implements the b-HiVE error models

Data Set: b-HiVE Hardware Characterization Dataset, a raw dataset of full-analog HSIM and SPICE simulations of industrial strength 64-bit integer ALUs, integer multipliers, bitwise logic operations, FP adders, FP multipliers, and FP dividers from OpenSparc T1 across voltage domains, along with controlled value correlation experiments (2015)

The project website with links to released software and datasets is here.

 

Towards Energy-Efficient Photonic Interconnects
Y. Demir and N. Hardavellas
In Proceedings of SPIE, Optical Interconnects XV, San Francisco, CA, February 2015
Also selected to appear in SPIE Green Photonics

 

Towards Energy Proportional Nanophotonic Interconnects

Y. Demir and N. Hardavellas

In 4th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2015

 

SeaFire: Specialized Computing on Dark Silicon with Heterogeneous Hardware Multi-Pipelining

G. Tziantzioulis, K. Hale, B. Pashaj, N. Hardavellas and P. Dinda

In 4th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2015

 

b-HiVE: A Bit-Level History-Based Error Model with Value Correlation for Voltage-Scaled Integer and Floating Point Units

G. Tziantzioulis, A. M. Gok, S M Faisal, N. Hardavellas, S. Ogrenci-Memik and S. Parthasarathy

In 4th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2015

 

2014

LaC: Integrating Laser Control in a Photonic Interconnect
Y. Demir and N. Hardavellas
In Proceedings of the IEEE Photonics Conference (IPC), pp. 28–29, La Jolla, CA, October 2014

 

EcoLaser: An Adaptive Laser Control for Energy-Efficient On-Chip Photonic Interconnects
Y. Demir and N. Hardavellas
In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 3–8, La Jolla, CA, August 2014

Acceptance rate for full papers 23%

 

Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects
Y. Demir, Y. Pan, S. Song, N. Hardavellas, G. Memik and J. Kim
In Proceedings of the ACM International Conference on Supercomputing (ICS), pp. 303–312, Munich, Germany, June 2014

Acceptance rate 20%

 

LaC: Integrating Laser Control in a Photonic Interconnect

Y. Demir and N. Hardavellas

Technical Report NU-EECS-14-03, Northwestern University, Evanston, IL, April 2014

 

EcoLaser: An Adaptive Laser Control for Energy Efficient On-Chip Photonic Interconnects

Y. Demir and N. Hardavellas

Technical Report NU-EECS-14-02, Northwestern University, Evanston, IL, April 2014

 

EcoLaser: An Adaptive Laser Control for Energy Efficient On-Chip Photonic Interconnects

Y. Demir and N. Hardavellas

In 3rd Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2014

 

Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects

Y. Demir, Y. Pan, S. Song, N. Hardavellas, G. Memik and J. Kim

In 3rd Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2014

 

Elastic Fidelity: Trading-Off Computational Accuracy for Energy Efficiency

G. Tziantzioulis, A. M. Gok, S. M. Faisal, N. Hardavellas, S. Memik, and S. Parthasarathy

In 3rd Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2014

 

2013

The Impact of Dynamic Directories on Multicore Interconnects
M. Schuchhardt, A. Das, N. Hardavellas, G. Memik, and A. Choudhary
IEEE Computer, Special Issue on Multicore Memory Coherence, Vol. 46(10), pp. 32–39, October 2013

 

Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects

Y. Demir, Y. Pan, S. Song, N. Hardavellas, J. Kim, and G. Memik

Technical Report NU-EECS-13-08, Northwestern University, Evanston, IL, July 2013

 

Elastic Fidelity: Trading-Off Computational Accuracy for Energy Reduction

G. Tziantzioulis, A. M. Gok, S. M. Faisal, N. Hardavellas, S. Memik, and S. Parthasarathy

In 2nd Greater Chicago Area Systems Research Workshop (GCASR), Evanston, IL, April 2013

 

Galaxy: Pushing the Power and Bandwidth Walls with Optically Connected Disintegrated Processors

Y. Demir and N. Hardavellas

In 2nd Greater Chicago Area Systems Research Workshop (GCASR), Evanston, IL, April 2013

 

2012

Towards a Schlieren Camera

B. Pattabiraman, R. Morton, A. Grabenhofer, N. Hardavellas, J. Tumblin, and V. Gopal

8th Annual Mid-West Graphics Workshop (MIDGRAPH), Chicago, IL, December 2012

 

Load Balancing for Processing Spatio-Temporal Queries in Multi-Core Settings

A. Yaagoub, G. Trajcevski, P. Scheuermann, and N. Hardavellas

11th International ACM Workshop on Data Engineering for Wireless and Mobile Access (MobiDE), co-located with ACM SIGMOD International Conference on Management of Data and ACM SIGMOD-SIGACT-SIGART Symposium on Principles of Database Systems (ACM SIGMOD/PODS), Scottsdale, AZ, May 2012

 

The Rise and Fall of Dark Silicon
N. Hardavellas
USENIX ;login:, Vol. 37, No. 2, pp. 7–17, April 2012

Invited Paper

 

Dynamic Directories: Reducing On-Chip Interconnect Power in Multicores
A. Das, M. Schuchhardt, N. Hardavellas, G. Memik, and A. Choudhary
In Proceedings of Design, Automation, and Test in Europe (DATE), pp. 479–484, Dresden, Germany, March 2012

Acceptance rate 25%

 

2011

Elastic Fidelity: Trading-off Computational Accuracy for Energy Reduction

S. Roy, T. Clemons, S. M. Faisal, K. Liu, N. Hardavellas, and S. Parthasarathy

Technical Report NWU-EECS-11-02, Northwestern University, Evanston, IL, February 2011

Indexed at arXiv:1111.4279 [cs.AR], November 2011

 

Toward Dark Silicon in Servers
N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki
IEEE Micro, Special Issue on Big Chips, Vol. 31(4), pp. 6–15, July/August 2011

IEEE Micro Spotlight Paper at Computing Now, February 2012

 

Exploiting Dark Silicon for Energy Efficiency

N. Hardavellas

NSF Workshop on Sustainable Energy-Efficient Data Management (SEEDM), National Science Foundation, Arlington, VA, USA, May 2011

 

Elastic Fidelity: Trading-off Computational Accuracy for Energy Reduction

S. Roy, T. Clemons, S. M. Faisal, K. Liu, N. Hardavellas, and S. Parthasarathy

In 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Newport Beach, California, March 2011 (poster)

 

Hardware/Software Techniques for DRAM Thermal Management
S. Liu, B. Leung, A. Neckar, S. Ogrenci-Memik, G. Memik, and N. Hardavellas
The Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 479–484, San Antonio, Texas, February 2011

Acceptance rate 18%

 

2010

PAD: Power-Aware Directory Placement in Distributed Caches

A. Das, M. Schuchhardt, N. Hardavellas, G. Memik, and A. Choudhary

Technical Report NWU-EECS-10-11, Northwestern University, Evanston, IL, December 2010

 

Exploring Benefits and Designs of Optically-Connected Disintegrated Processor Architecture

Y. Pan, Y. Demir, N. Hardavellas, J. Kim, and G. Memik

Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS)

co-located with the 43rd International Symposium on Microarchitecture (MICRO), Atlanta, GA, December 2010

 

Data-Oriented Transaction Execution
I. Pandis, R. Johnson, N. Hardavellas, and A. Ailamaki
Proceedings of the VLDB Endowment (PVLDB), Vol. 3(1), pp. 928–939, August 2010

 

Data-Oriented Transaction Execution
I. Pandis, R. Johnson, N. Hardavellas, and A. Ailamaki
9th Hellenic Data Management Symposium (HDMS), Ayia Napa, Cyprus, July 2010

 

The Path Forward: Specialized Computing in the Datacenter

N. Hardavellas, M. Ferdman, A. Ailamaki, and B. Falsafi
2nd Workshop on Architectural Considerations for Large Datacenters (ACLD)

co-located with the 37th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 2010

 

Power Scaling: the Ultimate Obstacle to 1K-Core Chips

N. Hardavellas, M. Ferdman, A. Ailamaki, and B. Falsafi

Technical Report NWU-EECS-10-05, Northwestern University, Evanston, IL, March 2010

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures
N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki

IEEE Micro, Vol. 30(1), pp. 20–28, January/February 2010

IEEE Micro Top Picks from Computer Architecture Conferences


Data-Oriented Transaction Execution
I. Pandis, R. Johnson, N. Hardavellas, and A. Ailamaki
Technical Report CMU-CS-10-101, Computer Science Department, Carnegie Mellon University, Pittsburgh, PA, January 2010

 

2009

Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches
N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki
In Proceedings of the 36th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 184–195, Austin, TX, June 2009

Acceptance rate 20%

One of the 12 computer architecture papers of 2009 selected for the IEEE Micro Top Picks special issue

 

Shore-MT: A Scalable Storage Manager for the Multicore Era
R. Johnson, I. Pandis, N. Hardavellas, A. Ailamaki, and B. Falsafi
In Proceedings of the 12th International Conference on Extending Database Technology (EDBT), pp. 24–35, Saint-Petersburg, Russia, March 2009

Acceptance rate 33%

Software: Shore-MT, a scalable storage manager for the multicore era

 

Operator-Level Parallelism
N. Hardavellas and I. Pandis
Encyclopedia of Database Systems, pp. 1981–1985, L. Liu and M. T. Ozsu (Eds.), Springer, 2009

 

Execution Skew
N. Hardavellas and I. Pandis
Encyclopedia of Database Systems, pp. 1079, L. Liu and M. T. Ozsu (Eds.), Springer, 2009

 

Inter-Query Parallelism
N. Hardavellas and I. Pandis
Encyclopedia of Database Systems, pp. 1566–1567, L. Liu and M. T. Ozsu (Eds.), Springer, 2009

 

Intra-Query Parallelism
N. Hardavellas and I. Pandis
Encyclopedia of Database Systems, pp. 1567–1568, L. Liu and M. T. Ozsu (Eds.), Springer, 2009

 

Stop-and-Go Operator
N. Hardavellas and I. Pandis
Encyclopedia of Database Systems, pp. 2794, L. Liu and M. T. Ozsu (Eds.), Springer, 2009

 

2008

R-NUCA: Data Placement in Distributed Shared Caches
N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki
Technical Report CALCM-TR-2008-001, Computer Architecture Lab, Carnegie Mellon University, Pittsburgh, PA, December 2008

 

Shore-MT: A Quest for Scalability in the Many-Core Era
R. Johnson, I. Pandis, N. Hardavellas, and A. Ailamaki
Technical Report CMU-CS-08-114, Computer Science Department, Carnegie Mellon University, Pittsburgh, PA, 2008

 

To Share Or Not To Share?
R. Johnson, N. Hardavellas, I. Pandis, N. Mancheril, S. Harizopoulos, K. Sabirli, A. Ailamaki, and B. Falsafi
7th Hellenic Data Management Symposium (HDMS), Heraklion, Crete, Greece, July 2008

 

2007

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
J. Kim, N. Hardavellas, K. Mai, B. Falsafi, and J. C. Hoe
In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 197–209, Chicago, IL, December 2007

Acceptance rate 21%

 

To Share Or Not To Share?
R. Johnson, N. Hardavellas, I. Pandis, N. Mancheril, S. Harizopoulos, K. Sabirli, A. Ailamaki, and B. Falsafi
In Proceedings of the 33rd International Conference on Very Large Data Bases (VLDB), pp. 351–362, Vienna, Austria, September 2007

Acceptance rate 16%

 

An Analysis of Database System Performance on Chip Multiprocessors
N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, S. Harizopoulos, A. Ailamaki, and B. Falsafi
6th Hellenic Data Management Symposium (HDMS), Athens, Greece, July 2007

 

Scheduling Threads for Constructive Cache Sharing on CMPs
S. Chen, P. B. Gibbons, M. Kozuch, V. Liaskovitis, A. Ailamaki, G. E. Blelloch, B. Falsafi, L. Fix, N. Hardavellas, T. C. Mowry, and C. Wilkerson
In Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pp. 105–115, San Diego, CA, June 2007

Acceptance rate 28%

 

Database Servers on Chip Multiprocessors: Limitations and Opportunities
N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, A. Ailamaki, and B. Falsafi
In Proceedings of the 3rd Biennial Conference on Innovative Data Systems Research (CIDR), pp. 79–87, Asilomar, CA, January 2007

Acceptance rate 44%

 

2006

An Analysis of Database System Performance on Chip Multiprocessors
N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, S. Harizopoulos, A. Ailamaki, and B. Falsafi
Technical Report CMU-CS-06-153, Computer Science Department, Carnegie Mellon University, Pittsburgh, PA, 2006

 

Parallel Depth First vs. Work Stealing Schedulers on CMP Architectures
V. Liaskovitis, S. Chen, P. B. Gibbons, A. Ailamaki, G. E. Blelloch, B. Falsafi, L. Fix, N. Hardavellas, M. Kozuch, T. C. Mowry, and C. Wilkerson
In Proceedings of the 18th Annual ACM International Symposium on Parallelism in Algorithms and Architectures (SPAA), pp. 330, Cambridge, MA, August 2006

Acceptance rate 45%

 

Simultaneous Pipelining in QPipe: Exploiting Work Sharing Opportunities Across Queries
D. Dash, K. Gao, N. Hardavellas, S. Harizopoulos, R. Johnson, N. Mancheril, I. Pandis, V. Shkapenyuk, and A. Ailamaki
Demonstration, In Proceedings of the 22nd International Conference on Data Engineering (ICDE), Atlanta, GA, April 2006

Acceptance rate 19%
Best Demonstration Award

2005

Store-Ordered Streaming of Shared Memory
T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, C. Gniady, A. Ailamaki, and B. Falsafi
In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 75–86, Saint Louis, MO, September 2005

Acceptance rate 25%

 

Temporal Streaming of Shared Memory
T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi
In Proceedings of the 32nd ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 222–233, Madison, WI, June 2005

Acceptance rate 23%

 

2004

SORDS: Just-In-Time Streaming of Temporally-Correlated Shared Data
T. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, C. Gniady, A. Ailamaki, and B. Falsafi
Technical Report CALCM-TR-2004-002, Computer Architecture Lab, Carnegie Mellon University, Pittsburgh, PA, November 2004

 

Memory Coherence Activity Prediction in Commercial Workloads
S. Somogyi, T. F. Wenisch, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi
3rd Workshop on Memory Performance Issues (WMPI), pp. 37–45, Munich, Germany, June 2004

 

SimFlex: a Fast, Accurate, Flexible Full-System Simulation Framework for Performance Evaluation of Server Architecture
N. Hardavellas, S. Somogyi, T. F. Wenisch, R. E. Wunderlich, S. Chen, J. Kim, B. Falsafi, J. C. Hoe, and A. Nowatzyk
ACM SIGMETRICS Performance Evaluation Review (PER) Special Issue on Tools for Computer Architecture Research, Vol. 31(4), pp. 31–35, March 2004

Software: Flexus, a scalable, full-system, cycle-accurate simulation framework of multicore and multiprocessor systems

 

2003 and prior

Adaptive Dirty-Block Purging
S. C. Steely Jr. and N. Hardavellas
U.S. patent 6,493,801, December 2002

Apparatus and Method for Maintaining Data Coherence Within a Cluster of Symmetric Multiprocessors
L. I. Kontothanassis, M. L. Scott, N. Hardavellas, G. C. Hunt, R. J. Stets, and S. Dwarkadas
U.S. patent 6,341,339, January 2002

 

The Implementation of Cashmere
R. J. Stets, D. Chen, S. Dwarkadas, N. Hardavellas, G. C. Hunt, L. Kontothanassis, G. Magklis, S. Parthasarathy, U. Rencuzogullari, and M. L. Scott
Technical Report TR 723, Computer Science Department, University of Rochester, Rochester, NY, December 1999

Cashmere-VLM: Remote Memory Paging for Software Distributed Shared Memory
S. Dwarkadas, N. Hardavellas, L. Kontothanassis, R. Nikhil, and R. Stets
In Proceedings of the 13th IEEE/ACM International Parallel Processing Symposium (IPPS), pp. 153–159, San Juan, Puerto Rico, April 1999

Acceptance rate 43%

Software Cache Coherence with Memory Scaling
N. Hardavellas, L. Kontothanassis, R. Nikhil, and R. J. Stets
7th Workshop on Scalable Shared Memory Multiprocessors (SSMM), Barcelona, Spain, June 1998

Understanding the Performance of DSM Applications
W. Meira Jr., T. J. LeBlanc, N. Hardavellas, and C. Amorim
Communication and Architectural Support for Network-Based Parallel Computing (CANPC), D. Panda and C. Stunkel Eds., Lecture Notes in Computer Science, Vol. 1199/1997, pp. 198–211, Springer Berlin/Heidelberg, February 1997, DOI: 10.1007/3-540-62573-9_15

 

Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network
R. J. Stets, S. Dwarkadas, N. Hardavellas, G. C. Hunt, L. Kontothanassis, S. Parthasarathy, and M. L. Scott
In Proceedings of the 16th ACM Symposium on Operating Systems Principles (SOSP), pp. 170–183, Saint Malo, France, October 1997

Acceptance rate 17%

VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
L. Kontothanassis, G. C. Hunt, R. J. Stets, N. Hardavellas, M. Cierniak, S. Parthasarathy, W. Meira Jr., S. Dwarkadas, and M. L. Scott
In Proceedings of the 24th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 157–169, Denver, CO, June 1997

Acceptance rate 20%

 

Efficient Use of Memory Mapped Interfaces for Shared Memory Computing
N. Hardavellas, G. C. Hunt, S. Ioannidis, R. J. Stets, S. Dwarkadas, L. Kontothanassis, and M. L. Scott
In IEEE CS Technical Committee on Computer Architecture (TCCA) Special Issue on Distributed Shared Memory, pp. 28–33, March 1997

 

VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
L. Kontothanassis, G. C. Hunt, R. J. Stets, N. Hardavellas, M. Cierniak, S. Parthasarathy, W. Meira Jr, S. Dwarkadas, and M. L. Scott
Technical Report TR 643, Computer Science Department, University of Rochester, Rochester, NY, November 1996

The Implementation of Cashmere
M. L. Scott, W. Li, L. Kontothanassis, G. C. Hunt, M. Michael, R. J. Stets, N. Hardavellas, W. Meira Jr., A. Poulos, M. Cierniak, S. Parthasarathy, and M. Zaki
6th Workshop on Scalable Shared Memory Multiprocessors (SSMM), Boston, MA, October 1996

 

Contention in Counting Networks
C. Busch, N. Hardavellas, and M. Mavronicolas
In Proceedings of the 13th ACM Annual Symposium on Principles of Distributed Computing (PODC), Los Angeles, CA, August 1994

Notes on Sorting and Counting Networks
N. Hardavellas, D. Karakos, and M. Mavronicolas
Distributed Algorithms (WDAG), A. Schiper Ed., Lecture Notes in Computer Science, Vol. 725/1993, pp. 234–248, Springer Berlin/Heidelberg, September 1993, DOI: 10.1007/3-540-57271-6_39

 

Notes on Sorting and Counting Networks
N. Hardavellas, D. Karakos, and M. Mavronicolas
Technical Report FORTH-ICS/TR-092, Institute of Computer Science, Foundation for Research and Technology - Hellas, Heraklion, Crete, Greece, July 1993