EECS 303 Advanced Digital Design

Time & Place

TTh 330-450pm TCH *L221*


Prof. Hai Zhou
haizhou AT northwestern dot edu
L461 Tech Institute
(847) 491-4155
Office Hours: T 2-3pm


Peng Kang
Office Hours: Th 930-1130 M314


CATALOG DESCRIPTION: Overview of digital design; two level minimization and implementation using PLAs/PALs; combinational logic implementation technologies; delays, timing and hazards in digital logic; multilevel logic synthesis; CAD tools for logic minimization and synthesis; arithmetic logic circuits such as adders, multipliers; memory elements and clocking; registers, counters, shifters; random access memory and read only memory; sequential logic design; finite state machine optimization and state assignment; introduction to VHDL; VHDL structural modeling; VHDL behavioral modeling; case studies in VHDL.


EECS 203

By Topic:

  • Number system and representation;
  • Logic simplification by Boolean Algebra and K-map;
  • Combinational implementation using AND, OR, NOT, NAND, NOR;
  • MSI components such as adders, decoders, and multiplexers;
  • Exposure to memory elements, flip-flops, registers, and counters.
  • Text

  • Mano & Kime. Logic & Computer Design Fundamentals, Pearson/Prentice Hall.
  • Policy

    Grades: 25% Homework     25% Labs     20% Midterm      30% Final
    Late: -10% per day

    Reading materials

    0. EWD340: The humble programmer Pondering about programming--the central task of computing science--Dijkstra urges us "to approach the task with a full appreciation of its tremendous difficulty, ..., stick to modest and elegant programming languages, ..., respect the intrinsic limitations of the human mind and approach the task as Very Humble Programmers." Even though we approach hardware design instead of programming, we must prepare us with the same humble minds.

    Lecture schedule (ppt files are given for your reference)

  • Week 1: Introduction to logic design: class administration, digital design methodology, introduction to Mentor Graphics tools, review of Boolean algebra and two level minimization: logic gates, Boolean algebra review. (READINGS M&K Chapters 1&2)  Lec01.ppt
  • Week 2: Memory elements and clocking: latches, flip-flops, timing issues, setup and hold times, registers, counters. (READINGS M&K Chapter 4) Lec08.ppt   Lec09.ppt
  • Week 3: Combinational logic implementation technologies: programmable logic arrays, MOS transistor logic, multiplexers, decoders, ROMS. (READINGS M&K Chapter 3) Lec04.ppt
  • Week 4: Arithmetic Logic Circuits: Adders, ripple carry, carry lookahead, carry select adders, combinational array multipliers, ALUs, general function units. (READINGS M&K Chapters 3&7) Lec06.ppt
  • Week 5: Finite State Machine Design: Review of state machine design, Moore/Mealy machine, finte state machine word problems. Finite State Machine Optimization: state minimization algorithms, row matching method, implicict chart method, paper and pencil methods for state assignment, one-hot encodings. (READINGS M&K Chapter 4) Lec10.ppt Lec11.ppt
  • Week 6: Delays and timing in multilevel logic: gate delays, timing waveforms, static/dynamic hazards and glitches, designs to avoid hazards. (READINGS Materials) Lec07.ppt
  • Week 7: Introduction to VHDL: VHDL language basics, interface, architecture body, behavioral VHDL, process statements, delay models. VHDL Structural Modeling: Review of VHDL, structural VHDL modeling, use of hierarchy, combinational designs, component instantiation, concurrent statments, test benches. (READINGS Materials) Lec12.ppt     Lec13.ppt
  • Week 8: VHDL Modeling of Sequential Machines: Describing sequential behavior in VHDL, latches, flip flops, FSMs, Synthesis using VHDL, packages in VHDL. (READINGS Materials) Lec14.ppt
  • Week 9-10: Asynchronous System Design. (READING Materials)
  • Labs (due before the class on each date)

    1. (due 10/6) Introduction to the use of the Mentor Graphics tools--Design Architect schematic entry system, the Quicksim logic simulator.  lab1.pdf
    2. (due 10/20) Use of the Mentor Graphics Tools to design a 4-bit GCD computer, learn to design sequential circuit and simulate it. lab2.pdf
    3. (due 11/8) Speeding up the GCD computer. lab3.pdf
    4. (due 11/22) Use of VHDL in the Mentor Graphics tools, design of 8-bit finite state machine using behavioral and structural VHDL, VHDL simulation. lab4.pdf

    Homework (due before the class on each date)

    1. (due 9/29)Two level minimization and implementation hw1.pdf
    2. (due 10/13) Memory, timing, and sequential circuits hw2.pdf
    3. Midterm will be on Oct. 20. Here is the last year's midterm.
    4. (due 11/1) Arithmetic circuits hw3.pdf
    5. (due 11/15) VHDL hw4.pdf
    6. (due 11/29) Asynchronous circuits hw5.pdf


    Please check back often to this page ( for updates and course material download.