TTh 330-450pm TCH *L221*
Prof. Hai Zhou
haizhou AT northwestern dot edu
L461 Tech Institute
Office Hours: T 2-3pm
Peng Kang email@example.com
Office Hours: Th 930-1130 M314
CATALOG DESCRIPTION: Overview of digital design; two level minimization and implementation using PLAs/PALs; combinational logic implementation technologies; delays, timing and hazards in digital logic; multilevel logic synthesis; CAD tools for logic minimization and synthesis; arithmetic logic circuits such as adders, multipliers; memory elements and clocking; registers, counters, shifters; random access memory and read only memory; sequential logic design; finite state machine optimization and state assignment; introduction to VHDL; VHDL structural modeling; VHDL behavioral modeling; case studies in VHDL.
Number system and representation; Logic simplification by Boolean Algebra and K-map; Combinational implementation using AND, OR, NOT, NAND, NOR; MSI components such as adders, decoders, and multiplexers; Exposure to memory elements, flip-flops, registers, and counters.
Mano & Kime. Logic & Computer Design Fundamentals, Pearson/Prentice Hall.
Grades: 25% Homework 25% Labs 20% Midterm 30% Final
Late: -10% per day
0. EWD340: The humble programmer Pondering about programming--the central task of computing science--Dijkstra urges us "to approach the task with a full appreciation of its tremendous difficulty, ..., stick to modest and elegant programming languages, ..., respect the intrinsic limitations of the human mind and approach the task as Very Humble Programmers." Even though we approach hardware design instead of programming, we must prepare us with the same humble minds.
Week 1: Introduction to logic design: class administration, digital design methodology, introduction to Mentor Graphics tools, review of Boolean algebra and two level minimization: logic gates, Boolean algebra review. (READINGS M&K Chapters 1&2) Lec01.ppt Week 2: Memory elements and clocking: latches, flip-flops, timing issues, setup and hold times, registers, counters. (READINGS M&K Chapter 4) Lec08.ppt Lec09.ppt Week 3: Combinational logic implementation technologies: programmable logic arrays, MOS transistor logic, multiplexers, decoders, ROMS. (READINGS M&K Chapter 3) Lec04.ppt Week 4: Arithmetic Logic Circuits: Adders, ripple carry, carry lookahead, carry select adders, combinational array multipliers, ALUs, general function units. (READINGS M&K Chapters 3&7) Lec06.ppt Week 5: Finite State Machine Design: Review of state machine design, Moore/Mealy machine, finte state machine word problems. Finite State Machine Optimization: state minimization algorithms, row matching method, implicict chart method, paper and pencil methods for state assignment, one-hot encodings. (READINGS M&K Chapter 4) Lec10.ppt Lec11.ppt Week 6: Delays and timing in multilevel logic: gate delays, timing waveforms, static/dynamic hazards and glitches, designs to avoid hazards. (READINGS Materials) Lec07.ppt Week 7: Introduction to VHDL: VHDL language basics, interface, architecture body, behavioral VHDL, process statements, delay models. VHDL Structural Modeling: Review of VHDL, structural VHDL modeling, use of hierarchy, combinational designs, component instantiation, concurrent statments, test benches. (READINGS Materials) Lec12.ppt Lec13.ppt Week 8: VHDL Modeling of Sequential Machines: Describing sequential behavior in VHDL, latches, flip flops, FSMs, Synthesis using VHDL, packages in VHDL. (READINGS Materials) Lec14.ppt Week 9-10: Asynchronous System Design. (READING Materials)
Please check back often to this page (www.eecs.northwestern.edu/~haizhou/303/) for updates and course material download.