M314, Technological Institute
Department of Electrical Engineering and Computer Science
1. Static timing analysis, Gate Sizing, Statistical optimization
2. Mathematical modeling of VLSI
3. Reconfigurable logic: Power and Timing issues in FPGA
Doctoral in Computer Engineering (Currently Pursuing)
Department of Electrical and Computer Engineering,
Bachelor of Technology (B.Tech, Hons) (2004)
Department of Computer Science and Engineering,
Research & Training Experience
Department of Electrical Engineering and Computer Science.
March 2005 – Present
Research Advisor – Prof. Hai Zhou
1. Static Timing Analysis with Crosstalk effects: Considering parasitic effects such as crosstalk, the present approaches to timing analysis is time consuming. This project deals with developing speed-up techniques to do timing analysis taking into account the crosstalk effects that are bound to appear in deep submicron technologies. Complex timing and coupling models are explored in this project to get realistic timing analysis for 90nm technology nodes and beyond. Relevant papers : [2,3]
1. Strategic CAD
Lab, Intel Corporation,
2. High performance
IC Design and Analysis Lab,
3. Faraday Technology
2. Accurate and efficient gate sizing: Traditional gate sizing ignored the impact of gate size alteration on the timing properties of each arc associated with the gate. In this research we develop models to capture the timing information in gate sizing accurately. We are developing efficient flow based solver for sub-gradient computation in traditional LR-based gate sizing.
3. Timing Analysis of un-buffered sequentials: Un-buffered latches are key elements of modern day high performance microprocessor design due to their property to lower delay and power consumption. This research explores the effect of un-buffered sequentials on performance verification and timing optimization.
4. Statistical Optimization: As a course project I extended the linear delay model used for statistical timing analysis to a quadratic model and found closed form solutions for the quadratic model to be used in Statistical Timing Analysis framework. Future direction of this project will involve statistical optimization considering crosstalk.
September 2004 – February 2005
Project Advisor – Prof. Seda Memik
1. Power Aware Reconfigurable Logic: This project proposed an approach to save the leakage power in FPGAs. Relevant paper : 
2. Analysis of Routing Pattern of FPGAs: I developed a tool based on VPR for the analysis of routing patterns in FPGAs. Please refer my website for the source code.
Graduate Summer Intern
Strategic CAD Lab, Intel Corporation.
June 2006 – September 2006
Project Advisors – Kip Killpack and Dr. Chandramouli Kashyap
Manager – Dr. Noel Menezes
Project: This project presented a novel iterative algorithm for pessimism reduction in static timing analysis in presence of crosstalk using logic and timing filtering. An accurate coupling model based on arrival times and slews is presented which invalidates the monotonic property of Miller Coupling Factor computation as claimed by earlier research. In this research we also derive a sensitivity based metric to select aggressors for logic analysis as logic analysis is often run-time inefficient. Relevant paper: 
Graduate Summer Intern
Calypto Design Systems Inc.
June 2005 – September 2005
Project Advisors – Rajat Subhra Mukerjee, Abhishek Ranjan, Dr. Sumit Roy and Dr. Venky Ramachandran
1. Enhancements to SLEC Optimization engine like propagating constants across different types, optimization of scan-latch designs and strength reductions.
2. For timing analysis of system level designs, fast generation of accurate timing macromodel for system level blocks are essential. I developed an efficient timing macromodeling algorithm for word level static timing analysis. The algorithm is integrated to the static timer at Calypto. Relevant paper : 
B.Tech Senior Year Student
Department of Computer Science and Engineering
August 2003-May 2004
Project Advisor – Prof. Anupam Basu and Prof. Arobinda Gupta
This project dealt with developing text-to-speech synthesis software called Embedded Shurti for handheld devices running Windows CE. This extended the Shruti software developed by MediaLab, IIT Kharagpur into the domain of Pocket-PCs.
Undergraduate Summer Intern
Tata Research Design and Development Centre
May 2003-July 2003
Project Advisor – Dr. Prahlad Sampath
Developed a binary decision diagram solver to solve live variable analysis of high level languages.
B.Tech Junior Year Student
Department of Computer Science and Engineering
May 2002-May 2003
1. Advanced VLSI Laboratory, Indian Institute of Technology, Kharagpur
16th Dec 2002- 20th Dec 2002
Attended a course on Advanced Computer Architecture by Prof. Trevor Mudge,
2. Continuing Education Program, Indian Institute of Technology, Kharagpur
22nd May 2002-7th June 2002
Attended a course on Object Oriented Programming in C++ and Visual C++
conducted by Mathematics department, IIT Kharagpur and secured an EX (Excellent)
Associated faculty: Dr. D Goswami
1. Somsubhra Mondal, Debasish Das
and Seda Memik. Hierarchical
LUT Structures for Leakage Power Reduction, Poster Paper, Proc. International
Symposium on FPGAs (FPGA 2005),
Debasish Das, Ahmed Shebaita, Hai
Zhou, Yehea Ismail and Kip Killpack. FA-STAC: A Framework for Fast
and Accurate Static Timing Analysis with Coupling, IEEE International
Conference on Computer Design,
Debasish Das, Ahmed Shebaita, Yehea
Ismail, Hai Zhou and Kip Killpack. Nostra-XTalk:
A Predictive Framework for Accurate Static
Timing Analysis in UDSM VLSI Circuits, ACM Great Lakes Symposium on VLSI,
4. Debasish Das, Kip Killpack, Chandramouli Kashyap, Abhijit Jas and Hai Zhou. Pessimism Reduction in Coupling Aware Static Timing Analysis Using Timing and Logic Filtering, Submitted to Design Automation Conference, 2007.
5. Debasish Das, Abhishek Ranjan, Sumit Roy and Venky Ramachandran, Efficient Timing Macromodeling for Word Level Static Timing Analysis, Internal Report, Calypto Design Systems Inc.
6. Debasish Das, Symbolic solver for live
variable analysis of high level design languages, accepted to IEEE Computer
Society Annual Symposium on VLSI,
GRE: Quantitative: 800/800 Verbal: 550/800 Analytical: 4.5/6.0
TOEFL: 270/300, TSE: 45/60
Graduate Courses (GPA = 3.9/4.0)
Electrical Engineering and Computer Science Courses: Computer Architecture, VLSI System Design, Introduction to VLSI CAD, Design and Analysis of High Speed ICs, Formal Techniques in Design and Verification of Digital Systems, Design and Analysis of Algorithms, Advanced Algorithms, Seminar on Computer Security and Information Assurance, Random Processes in Communications and Control – I, Advanced Computer Architecture – II, Numerical Methods for Engineers
Industrial Engineering and Management Sciences Courses: Mathematical Programming
Undergraduate Courses (GPA = 8.3/10.0)
Departmental Core: Programming and Data Structure, Discrete Structures, Switching Circuits and Logic Design, Design and Analysis of Algorithms, Computer Organization and Architecture, Formal Language and Automata Theory, Operating Systems, Computer Networks.
Departmental Electives: Microprocessors and Microcontrollers, Software Engineering, Electronic Design Automation, Artificial Intelligence, Compiler Construction, VLSI System Design, Embedded Systems, Applied Graph Theory, Low power circuits and systems, File Organization and Database Systems.
Other subjects: Basic Electronics, Electrical Technology, Electromagnetic Engineering, Semiconductor Devices, Probability and Statistics, Signals and Networks, Linear Algebra.
Fellowship and Achievements
1. Awarded travel grant to participate in Design Automation Summer School (DASS 2005) held in conjunction with Design Automation Conference, Anaheim, CA, USA 2005.
2. Walter P Murphy Fellowship awarded by the Department of Electrical and Computer Engineering, Robert R McCormick School of Engineering & Applied Sciences, Northwestern University for 2004-2005.
3. Was among the top 0.1% of students selected in IIT-JEE examinations (to get admission into Indian Institute of Technology).
4. Awarded merit certificate under National Scholarship Scheme from Director of Education, Government of India for outstanding performance in SSE Examinations.
1. Languages: C, C++, Java, Visual C++, VHDL/Verilog
2. Tools: AMPL, CPLEX,
TLA+, Mentor Graphics EDA Suite,
1. Reviewer: TCAD, DAC, ICCAD, ISPD, ISQED, TAU, VLSI India
2. Teaching Assistant for ECE203 (Introduction to Computer Engineering) Fall, Spring
2005, ECE231 (Advanced Programming for Computer Engineers) Winter 2006, ECE357 (Introduction to VLSI CAD) Fall 2006, EECS366 (Design and Analysis of Algorithms) Winter 2006.
3. Member of Bitwise 2004 organizing committee; Bitwise is an annual online
Programming contest organized by the Department of Computer Science and Engineering, IIT Kharagpur.
Awarded ‘B’ level certificate from National Cadet Corps,
References (Email address will be furnished upon request)
Professor Hai Zhou, Professor Yehea Ismail,
Department of EECS, Department of EECS,
Dr. Sumit Roy, Kip Killpack,
Head of Engineering, Strategic CAD Lab
Calypto Design Systems Inc,
Professor Ajit Pal,
Department of Computer Science and Engg,