Manuscripts

  • S. Mondal, D. Das, and S. O. Memik. Hierarchical LUT Structures for Leakage Power Reduction, Poster Paper. Proceedings of International Symposium on FPGAs(FPGA), Monterey, CA, 2005
  • D. Das. Symbolic solver for live variable analysis of high level design languages. Accepted to IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Karlsruhe, Germany, 2006
  • D. Das, A. Ranjan, S. Roy and V. Ramachandran. Efficient Timing Macromodeling for Word Level Static Timing Analysis. Internal Report, Calypto Design Systems Inc.
  • D. Das, A. Shebaita, H. Zhou, Y. Ismail, and K. Killpack. FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ppt IEEE International Conference on Computer Design (ICCD), San Jose, CA,2006.
  • D. Das, A. Shebaita, Y. Ismail, H. Zhou, and K. Killpack. Nostra-XTalk: a Predictive Framework for Accurate Static Timing Analysis in UDSM VLSI Circuits. ppt ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.
  • J. Wang, D. Das, and H. Zhou. Gate Sizing by Lagrangian Relaxation Revisited. Accepted to International Conference on Computer Aided Design (ICCAD), 2007.
  • D. Das, K. Killpack, C. Kashyap, A. Jas, and H. Zhou. Pessimism Reduction in Coupling Aware Static Timing Analysis Using Timing and Logic Filtering. Accepted to Asia and South Pacific Design Automation Conference (ASP-DAC), 2008.( Best paper award nominee )
  • J. Wang, D. Das, and H. Zhou. Gate Sizing by Lagrangian Relaxation Revisited. Under revision for Transactions on CAD (TCAD).
  • D. Das, A. Shebaita, H. Zhou, Y. Ismail and K. Killpack. FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. Under revision for Transactions on VLSI (TVLSI).
  • D. Das, K. Killpack, C. Kashyap, A. Jas and H. Zhou. Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. Under revision for Transactions on CAD (TCAD).
  • D. Das, W. Scott, S. Nazarian and H. Zhou. An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis. Abstract Accepted to ECM Workshop to be held in Conjunction with ICCAD 2008.
  • D. Das, W. Scott, S. Nazarian and H. Zhou. An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis. Full paper Accepted to IEEE International Symposium on Quality Electronic Design (ISQED) 2009.
  • D. Das, J. Wang and H. Zhou. iRetILP: An efficient incremental algorithm for min-period retiming under general delay model. To appear at ACM International Workshop on Timing Issues (TAU) 2009.
  • A. Shebaita, D. Das, D. Petranovic and Y. Ismail. A Novel Moment Based Framework For Accurate and Efficient Static Timing Analysis. Under revision for TCAD Transaction brief. SPICE sub-circuits used for experiments are available here .

    • Undergraduate Research Projects

    1.Summer project(2003,Industrial Training): Development of a BDD solver to solve live variable analysis equations. This project is done under the guidance of Dr. Prahlad Sampath, TRDDC ,TCS Pune. The complete project report is given below:

    Download the complete project report. pdf

    2. Final year BTech project : I developed a software called "Embedded Shruti" for my final year project. Embedded Shruti is the embedded (Pocket-PC) version of Shruti software developed by MediaLab,IIT Kharagpur. I ported it to Pocket-PC and the software is tested on a COMPAQ iPAQ Pocket PC. Those days PDAs were not common and they used to be heavy unlike a Treo! :-)

    The complete documentation of the software and the design flow which generated the product are given in my BTech thesis.

    Thesis : Frontpages Thesis